diff mbox series

[v4,5/5] rockchip: px30: add support for SFC for Odroid Go Advance

Message ID 20210615191046.11812-6-macroalpha82@gmail.com
State Superseded
Delegated to: Kever Yang
Headers show
Series rockchip_sfc: add support for Rockchip SFC | expand

Commit Message

Chris Morgan June 15, 2021, 7:10 p.m. UTC 
From: Chris Morgan <macromorgan@hotmail.com>

The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Additionally, a possible errata was found
while testing the Linux driver, in that setting the tx mode to 2
would cause erases and writes to sometimes fail. Setting the rx mode
to 2 and the tx mode to 1 for this reason, and to match the upcoming
changes to Linux.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 18 ++++++++++++++++++
 arch/arm/dts/rk3326-odroid-go2.dts         | 16 ++++++++++++++++
 2 files changed, 34 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 00767d2abd..d345f6a168 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -7,6 +7,16 @@ 
 	chosen {
 		u-boot,spl-boot-order = &sdmmc;
 	};
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdmmc;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		spi0 = &sfc;
+		spi_flash = "/spi@ff3a0000/flash@0";
+	};
 };
 
 &cru {
@@ -57,6 +67,14 @@ 
 	u-boot,spl-fifo-mode;
 };
 
+&sfc {
+	u-boot,dm-pre-reloc;
+
+	flash@0 {
+		u-boot,dm-pre-reloc;
+	};
+};
+
 &uart1 {
 	clock-frequency = <24000000>;
 	u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 8cd4688c49..4e3dceecbe 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -617,6 +617,22 @@ 
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <108000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 &tsadc {
 	status = "okay";
 };