@@ -591,6 +591,24 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (dwc->fladj_quirk && dwc->revision >= DWC3_REVISION_250A)
dwc3_frame_length_adjustment(dwc, dwc->fladj);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ /*
+ * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
+ * reliably support Rx Detect in P3 mode(P3 is the default
+ * setting). Therefore, some USB3.0 devices may not be detected
+ * reliably in Super Speed mode. So, USB controller to configure
+ * USB in P2 mode whenever the Receive Detect feature is required.
+ * whenever the Receive Detect feature is required.
+ */
+ if (dev_read_bool(dwc->dev, "snps,dis_rxdet_inp3_quirk")) {
+ if (dwc->dr_mode == USB_DR_MODE_HOST) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+ reg |= DWC3_GUSB3PIPECTL_DISRXDETP3;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ }
+ }
+#endif
+
return 0;
err1:
@@ -187,6 +187,7 @@
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3 BIT(28)
#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
Some NXP Layerscape platforms are required to disable receiver detection in P3 for correct detection of USB devices. If GUSB3PIPECTL(DISRXDETINP3) is set, Core will change PHY power state to P2 and then perform receiver detection. After receiver detection, Core will change PHY power state to P3. Same quirk would be added in dts file in future patches. Refer to Linux commit e58dd357741b (“usb: dwc3: add disable receiver detection in P3 quirk”) Signed-off-by: Ran Wang <ran.wang_1@nxp.com> --- drivers/usb/dwc3/core.c | 18 ++++++++++++++++++ drivers/usb/dwc3/core.h | 1 + 2 files changed, 19 insertions(+)