| Message ID | 20190925094811.21197-1-biwen.li@nxp.com |
|---|---|
| State | Accepted |
| Commit | 3f4bc67548595258764b6fb15717b17a05b6be58 |
| Delegated to: | Priyanka Jain |
| Headers | show |
| Series | [U-Boot,v2] armv7: ls102xa: Correct endianness of SCFG_SPARECR8 read | expand |
>-----Original Message----- >From: Biwen Li <biwen.li@nxp.com> >Sent: Wednesday, September 25, 2019 3:18 PM >To: albert.u.boot@aribaud.net; Prabhakar X ><prabhakar.kushwaha@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; >Priyanka Jain <priyanka.jain@nxp.com>; Ran Wang <ran.wang_1@nxp.com>; >Leo Li <leoyang.li@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com> >Cc: u-boot@lists.denx.de; Biwen Li <biwen.li@nxp.com> >Subject: [v2] armv7: ls102xa: Correct endianness of SCFG_SPARECR8 read > >The patch corrects endianness of register SCFG_SPARECR8 read >in_le32 -> in_be32 > >Signed-off-by: Biwen Li <biwen.li@nxp.com> >--- Slight update in subject and description. Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aaaf4..00b6ad48ce 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -72,7 +72,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * returns zero, so its value is saved to a scrachpad register to be * read, that is why we don't read it from register ippdexpcr1 itself. */ - ippdexpcr1 = in_le32(&scfg->sparecr[7]); + ippdexpcr1 = in_be32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
The patch corrects endianness of register SCFG_SPARECR8 read in_le32 -> in_be32 Signed-off-by: Biwen Li <biwen.li@nxp.com> --- Change in v2: - update subject and description arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)