diff mbox series

[U-Boot] armv8: fsl-layerscape: Make USB masters snoopable

Message ID 20190920093429.40435-1-ran.wang_1@nxp.com
State Accepted
Commit 3d23b6c5836c004c5f9a8281b03a2da98f20d9ff
Delegated to: Priyanka Jain
Headers show
Series [U-Boot] armv8: fsl-layerscape: Make USB masters snoopable | expand

Commit Message

Ran Wang Sept. 20, 2019, 9:34 a.m. UTC
Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write
snoop signal on LS1043A and LS1046A.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c                | 9 +++++++++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++
 2 files changed, 15 insertions(+)

Comments

Priyanka Jain Oct. 22, 2019, 4:37 a.m. UTC | #1
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Ran Wang
>Sent: Friday, September 20, 2019 3:04 PM
>To: Albert Aribaud <albert.u.boot@aribaud.net>; Prabhakar X
><prabhakar.kushwaha@nxp.com>
>Cc: open list <u-boot@lists.denx.de>; Ran Wang <ran.wang_1@nxp.com>
>Subject: [U-Boot] [PATCH] armv8: fsl-layerscape: Make USB masters snoopable
>
>Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
>SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop
>signal on LS1043A and LS1046A.
>
>Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
>---

Applied to fsl-qoriq master, awaiting upstream.

Thanks
priyankajain
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b508bc9..17c0502 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -636,10 +636,19 @@  void fsl_lsch2_early_init_f(void)
 #endif
 #endif
 	/* Make SEC reads and writes snoopable */
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+			SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+			SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+			SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+			SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+			SCFG_SNPCNFGCR_SATAWRSNP);
+#else
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 		     SCFG_SNPCNFGCR_SECWRSNP |
 		     SCFG_SNPCNFGCR_SATARDSNP |
 		     SCFG_SNPCNFGCR_SATAWRSNP);
+#endif
 
 	/*
 	 * Enable snoop requests and DVM message requests for
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b4b7c34..524961d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -409,6 +409,12 @@  struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
 #define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP	0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP	0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP	0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP	0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP	0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP	0x00004000
 
 /* RGMIIPCR bit definitions*/
 #define SCFG_RGMIIPCR_EN_AUTO		BIT(3)