| Message ID | 20190715194755.30428-1-simon.k.r.goldschmidt@gmail.com |
|---|---|
| State | Accepted, archived |
| Commit | cb20fe8f0b9ad9a9d48e243f7f72ab277b75a00f |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | [U-Boot,v4,1/4] arm: socfpga: rst: add register definition for cold reset | expand |
On 7/15/19 9:47 PM, Simon Goldschmidt wrote: > This adds a define for the bit in rstmgr's ctrl regiser that issues > a cold reset (we had a define for the warm reset bit only) in preparation > for a proper sysrese driver. > Applied all four, thanks.
Am 21.07.2019 um 12:45 schrieb Marek Vasut: > On 7/15/19 9:47 PM, Simon Goldschmidt wrote: >> This adds a define for the bit in rstmgr's ctrl regiser that issues >> a cold reset (we had a define for the warm reset bit only) in preparation >> for a proper sysrese driver. >> > > Applied all four, thanks. > Where did you push these? I see them at gitlab but not on github, is your github mirror dead then? Regards, Simon
On 7/23/19 8:37 PM, Simon Goldschmidt wrote: > Am 21.07.2019 um 12:45 schrieb Marek Vasut: >> On 7/15/19 9:47 PM, Simon Goldschmidt wrote: >>> This adds a define for the bit in rstmgr's ctrl regiser that issues >>> a cold reset (we had a define for the warm reset bit only) in >>> preparation >>> for a proper sysrese driver. >>> >> >> Applied all four, thanks. >> > > Where did you push these? I see them at gitlab but not on github, is > your github mirror dead then? https://github.com/marex/u-boot-socfpga/commits/master lists them just fine. Note that gitlab is the primary repo.
Am 23.07.2019 um 21:09 schrieb Marek Vasut: > On 7/23/19 8:37 PM, Simon Goldschmidt wrote: >> Am 21.07.2019 um 12:45 schrieb Marek Vasut: >>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote: >>>> This adds a define for the bit in rstmgr's ctrl regiser that issues >>>> a cold reset (we had a define for the warm reset bit only) in >>>> preparation >>>> for a proper sysrese driver. >>>> >>> >>> Applied all four, thanks. >>> >> >> Where did you push these? I see them at gitlab but not on github, is >> your github mirror dead then? > > https://github.com/marex/u-boot-socfpga/commits/master lists them just > fine. Note that gitlab is the primary repo. > Hmm, right. Sorry, I must have done something wrong. I have been using github as upstream because of denx.de performance issues. I have now switched to gitlab, let's see if performance stays as good as it is now :-) Regards, Simon
On 7/23/19 9:12 PM, Simon Goldschmidt wrote: > Am 23.07.2019 um 21:09 schrieb Marek Vasut: >> On 7/23/19 8:37 PM, Simon Goldschmidt wrote: >>> Am 21.07.2019 um 12:45 schrieb Marek Vasut: >>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote: >>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues >>>>> a cold reset (we had a define for the warm reset bit only) in >>>>> preparation >>>>> for a proper sysrese driver. >>>>> >>>> >>>> Applied all four, thanks. >>>> >>> >>> Where did you push these? I see them at gitlab but not on github, is >>> your github mirror dead then? >> >> https://github.com/marex/u-boot-socfpga/commits/master lists them just >> fine. Note that gitlab is the primary repo. >> > > Hmm, right. Sorry, I must have done something wrong. > > I have been using github as upstream It never was upstream, please don't use it as such. It's a necessary mirror for the travis CI, that's all.
Am 23.07.2019 um 21:26 schrieb Marek Vasut: > On 7/23/19 9:12 PM, Simon Goldschmidt wrote: >> Am 23.07.2019 um 21:09 schrieb Marek Vasut: >>> On 7/23/19 8:37 PM, Simon Goldschmidt wrote: >>>> Am 21.07.2019 um 12:45 schrieb Marek Vasut: >>>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote: >>>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues >>>>>> a cold reset (we had a define for the warm reset bit only) in >>>>>> preparation >>>>>> for a proper sysrese driver. >>>>>> >>>>> >>>>> Applied all four, thanks. >>>>> >>>> >>>> Where did you push these? I see them at gitlab but not on github, is >>>> your github mirror dead then? >>> >>> https://github.com/marex/u-boot-socfpga/commits/master lists them just >>> fine. Note that gitlab is the primary repo. >>> >> >> Hmm, right. Sorry, I must have done something wrong. >> >> I have been using github as upstream > > It never was upstream, please don't use it as such. It's a necessary > mirror for the travis CI, that's all. > Noted. Given the bad connectivity to the old denx git, I sometimes had no other option. I hope that's better now. Regards, Simon
On 7/23/19 9:27 PM, Simon Goldschmidt wrote: > Am 23.07.2019 um 21:26 schrieb Marek Vasut: >> On 7/23/19 9:12 PM, Simon Goldschmidt wrote: >>> Am 23.07.2019 um 21:09 schrieb Marek Vasut: >>>> On 7/23/19 8:37 PM, Simon Goldschmidt wrote: >>>>> Am 21.07.2019 um 12:45 schrieb Marek Vasut: >>>>>> On 7/15/19 9:47 PM, Simon Goldschmidt wrote: >>>>>>> This adds a define for the bit in rstmgr's ctrl regiser that issues >>>>>>> a cold reset (we had a define for the warm reset bit only) in >>>>>>> preparation >>>>>>> for a proper sysrese driver. >>>>>>> >>>>>> >>>>>> Applied all four, thanks. >>>>>> >>>>> >>>>> Where did you push these? I see them at gitlab but not on github, is >>>>> your github mirror dead then? >>>> >>>> https://github.com/marex/u-boot-socfpga/commits/master lists them just >>>> fine. Note that gitlab is the primary repo. >>>> >>> >>> Hmm, right. Sorry, I must have done something wrong. >>> >>> I have been using github as upstream >> >> It never was upstream, please don't use it as such. It's a necessary >> mirror for the travis CI, that's all. >> > > Noted. Given the bad connectivity to the old denx git, I sometimes had > no other option. I hope that's better now. I never had those problems, but the gitlab instance is on a different server. If you have connectivity issues, please report them.
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 42beaecdd6..6ad037e325 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -11,6 +11,7 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 /*
This adds a define for the bit in rstmgr's ctrl regiser that issues a cold reset (we had a define for the warm reset bit only) in preparation for a proper sysrese driver. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Series changes: 2 - separate this patch to the register descriptions from the actual sysreset driver patch --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 + 1 file changed, 1 insertion(+)