| Message ID | 20190523030546.16639-1-yinbo.zhu@nxp.com |
|---|---|
| State | Accepted |
| Delegated to: | Prabhakar Kushwaha |
| Headers | show |
| Series | [U-Boot,v5,1/2] armv8: fsl-lsch3: add clock support for the second eSDHC | expand |
> -----Original Message----- > From: Yinbo Zhu <yinbo.zhu@nxp.com> > Sent: Thursday, May 23, 2019 8:36 AM > To: York Sun <york.sun@nxp.com>; u-boot@lists.denx.de; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com> > Cc: Yinbo Zhu <yinbo.zhu@nxp.com>; Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei > Pan <jiafei.pan@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; Jagdish Gediya > <jagdish.gediya@nxp.com>; Andy Tang <andy.tang@nxp.com>; G.h. Gao > <guanhua.gao@nxp.com> > Subject: [PATCH v5 1/2] armv8: fsl-lsch3: add clock support for the second > eSDHC > > From: Yangbo Lu <yangbo.lu@nxp.com> > > Layerscape began to use two eSDHC controllers, for example, LS1028A. They > are same IP block with same reference clock. > This patch is to add clock support for the second eSDHC. > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> > --- > Change in v2: > Change in v3: > Remove non-TFA patch > Change in v4: > update the Copyright information > Change in v5: > Add NXP Copyright information > > Fixed copyright issue. This patch has been applied to fsl-qoriq master, awaiting upstream. --pk
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index bc268e207c..2d92d267a2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2014-2015, Freescale Semiconductor, Inc. + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP Semiconductors * * Derived from arch/power/cpu/mpc85xx/speed.c */ @@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..2f51155f21 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP Semiconductors * */ @@ -14,6 +15,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, };