diff mbox series

[U-Boot,v1,21/22] colibri_vf: use leveling evaluated by DDR validation tools

Message ID 20190215222039.10005-22-marcel@ziswiler.com
State Superseded
Delegated to: Stefano Babic
Headers show
Series colibri vybrid fixes, device tree enablement and driver model conversion | expand

Commit Message

Marcel Ziswiler Feb. 15, 2019, 10:20 p.m. UTC 
From: Stefan Agner <stefan.agner@toradex.com>

The DDR validation tool (which is part of Processor Expert) allows
to evaluate leveling parameters for CR105/CR106/CR110. Several
runs have been made with Colibri VF50 and VF61 and it seems to
evaluate very similar values. Use this values by default.

Note: The newly evaluated parameters seem to require CTLUPD_AREF
to be enabled!

Note 2: The tool also evaluated 6 as a new value for PHY02/18
GATE_CFG (Coarse adjust of gate open time). However, this seems
not to work in practise.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

---

 board/toradex/colibri_vf/colibri_vf.c | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 8c4909af54..87debf1360 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -27,6 +27,13 @@ 
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
+	{ DDRMC_CR79_CTLUPD_AREF(1), 79 },
+	/* sets manual values for read lvl. (gate) delay of data slice 0/1 */
+	{ DDRMC_CR105_RDLVL_DL_0(28), 105 },
+	{ DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
+	{ DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
+	{ DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
+
 	/* AXI */
 	{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
 	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },