diff mbox series

[U-Boot] sunxi: Fix memory 2-rank initialization for a33 cpu

Message ID 20181031190317.5134-1-michael@amarulasolutions.com
State Accepted
Commit aa09a071c3295011816c0e2f18532f61bc8b74f3
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series [U-Boot] sunxi: Fix memory 2-rank initialization for a33 cpu | expand

Commit Message

Michael Nazzareno Trimarchi Oct. 31, 2018, 7:03 p.m. UTC
When we initialize the memory we need to autodetect rank and size
but this can happen only if we send the proper reset to both
memory module including cke signal.
For this reason we need initialize the physical on both channel because
we need to presume that both are connected. This way let the CLKE to be
activated at the right time with the memory reset coming from the cpu

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Michael Nazzareno Trimarchi Nov. 2, 2018, 1:10 p.m. UTC | #1
Hi Maxime

On Wed, Oct 31, 2018 at 8:03 PM Michael Trimarchi
<michael@amarulasolutions.com> wrote:
>
> When we initialize the memory we need to autodetect rank and size
> but this can happen only if we send the proper reset to both
> memory module including cke signal.
> For this reason we need initialize the physical on both channel because
> we need to presume that both are connected. This way let the CLKE to be
> activated at the right time with the memory reset coming from the cpu
>
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Does enough clear?

Michael

> ---
>  arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> index d9aa0c6d7e..1da2727f98 100644
> --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
> +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> @@ -334,7 +334,7 @@ unsigned long sunxi_dram_init(void)
>         struct dram_para para = {
>                 .cs1 = 0,
>                 .bank = 1,
> -               .rank = 1,
> +               .rank = 2,
>                 .rows = 15,
>                 .bus_width = 16,
>                 .page_size = 2048,
> --
> 2.17.1
>
Maxime Ripard Nov. 5, 2018, 9:02 a.m. UTC | #2
On Wed, Oct 31, 2018 at 08:03:16PM +0100, Michael Trimarchi wrote:
> When we initialize the memory we need to autodetect rank and size
> but this can happen only if we send the proper reset to both
> memory module including cke signal.
> For this reason we need initialize the physical on both channel because
> we need to presume that both are connected. This way let the CLKE to be
> activated at the right time with the memory reset coming from the cpu
> 
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime
Michael Nazzareno Trimarchi Nov. 7, 2018, 5:13 p.m. UTC | #3
Hi Jagan

On Mon, Nov 5, 2018 at 10:02 AM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Wed, Oct 31, 2018 at 08:03:16PM +0100, Michael Trimarchi wrote:
> > When we initialize the memory we need to autodetect rank and size
> > but this can happen only if we send the proper reset to both
> > memory module including cke signal.
> > For this reason we need initialize the physical on both channel because
> > we need to presume that both are connected. This way let the CLKE to be
> > activated at the right time with the memory reset coming from the cpu
> >
> > Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
>

Can you test on a consumer board with A33? I have tested over
oscilloscope on my device

Michael

> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Jagan Teki Nov. 22, 2018, 7:54 a.m. UTC | #4
On Thu, Nov 1, 2018 at 12:33 AM Michael Trimarchi
<michael@amarulasolutions.com> wrote:
>
> When we initialize the memory we need to autodetect rank and size
> but this can happen only if we send the proper reset to both
> memory module including cke signal.
> For this reason we need initialize the physical on both channel because
> we need to presume that both are connected. This way let the CLKE to be
> activated at the right time with the memory reset coming from the cpu
>
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> ---

Applied to u-boot-sunxi/master
diff mbox series

Patch

diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index d9aa0c6d7e..1da2727f98 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -334,7 +334,7 @@  unsigned long sunxi_dram_init(void)
 	struct dram_para para = {
 		.cs1 = 0,
 		.bank = 1,
-		.rank = 1,
+		.rank = 2,
 		.rows = 15,
 		.bus_width = 16,
 		.page_size = 2048,