| Message ID | 20180611190051.6897-3-carlo@caione.org |
|---|---|
| State | Accepted |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | rk3288: veyron: Enable SDMMC when booting from SPI | expand |
> From: Carlo Caione <carlo@endlessm.com> > > The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it > is preventing the SDMMC to work correctly. Disable the JTAG function on > the assumption that a working SD has higher priority over JTAG. > > Signed-off-by: Carlo Caione <carlo@endlessm.com> > Reviewed-by: Simon Glass <sjg@chromium.org> > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > arch/arm/mach-rockchip/rk3288-board.c | 7 +++++++ > 1 file changed, 7 insertions(+) > Applied to u-boot-rockchip, thanks!
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 0365793009..bf24d8e074 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -307,6 +307,7 @@ U_BOOT_CMD( "" ); +#define GRF_SOC_CON0 0xff770244 #define GRF_SOC_CON2 0xff77024c int board_early_init_f(void) @@ -339,5 +340,11 @@ int board_early_init_f(void) } rk_setreg(GRF_SOC_CON2, 1 << 0); + /* + * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is + * cleared + */ + rk_clrreg(GRF_SOC_CON0, 1 << 12); + return 0; }