| Message ID | 20180512203020.17422-10-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | 421a21c53ae1520acdaf2b2c2544ba295b8fdd27 |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot,01/12] ARM: socfpga: Sync A10 clock manager binding parser | expand |
On Sun, May 13, 2018 at 4:30 AM, Marek Vasut <marex@denx.de> wrote: > From: Tien Fong Chee <tien.fong.chee@intel.com> > > Enable memory allocation in SPL for preparation to enable FAT > in SPL. Memory allocation is needed by FAT to work properly. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> > --- > include/configs/socfpga_common.h | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h > index a60da85499..acac4a7108 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -226,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > /* > * SPL > * > - * SRAM Memory layout: > + * SRAM Memory layout for gen 5: > * > * 0xFFFF_0000 ...... Start of SRAM > * 0xFFFF_xxxx ...... Top of stack (grows down) > * 0xFFFF_yyyy ...... Malloc area > * 0xFFFF_zzzz ...... Global Data > * 0xFFFF_FF00 ...... End of SRAM > + * > + * SRAM Memory layout for Arria 10: > + * 0xFFE0_0000 ...... Start of SRAM (bottom) > + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) > + * 0xFFEy_yyyy ...... Global Data > + * 0xFFEz_zzzz ...... Malloc area (grows up to top) > + * 0xFFE3_FFFF ...... End of SRAM (top) > */ > #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +/* SPL memory allocation configuration, this is for FAT implementation */ > +#ifndef CONFIG_SYS_SPL_MALLOC_START > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 > +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ > + CONFIG_SYS_SPL_MALLOC_SIZE + \ > + CONFIG_SYS_INIT_RAM_ADDR) > +#endif > +#endif > + > /* SPL SDMMC boot support */ > #ifdef CONFIG_SPL_MMC_SUPPORT > #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) > @@ -263,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > /* > * Stack setup > */ > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START > +#endif > > /* Extra Environment */ > #ifndef CONFIG_SPL_BUILD > -- > 2.16.2 Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a60da85499..acac4a7108 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -226,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * SPL * - * SRAM Memory layout: + * SRAM Memory layout for gen 5: * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_yyyy ...... Malloc area * 0xFFFF_zzzz ...... Global Data * 0xFFFF_FF00 ...... End of SRAM + * + * SRAM Memory layout for Arria 10: + * 0xFFE0_0000 ...... Start of SRAM (bottom) + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc area (grows up to top) + * 0xFFE3_FFFF ...... End of SRAM (top) */ #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +/* SPL memory allocation configuration, this is for FAT implementation */ +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SYS_INIT_RAM_ADDR) +#endif +#endif + /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) @@ -263,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Stack setup */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START +#endif /* Extra Environment */ #ifndef CONFIG_SPL_BUILD