@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
@@ -18,7 +19,13 @@
#include <fdtdec.h>
#include <linux/compat.h>
#include <asm/io.h>
+/*
+ * Some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) which don't implement
+ * generic clock framework and uses their clock_manager functions.
+ */
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || !CONFIG_IS_ENABLED(CLK)
#include <asm/arch/clock_manager.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -94,6 +101,7 @@ struct dw_spi_priv {
void __iomem *regs;
unsigned int freq; /* Default frequency */
unsigned int mode;
+ unsigned long bus_clk_rate;
int bits_per_word;
u8 cs; /* chip select pin */
@@ -176,14 +184,73 @@ static void spi_hw_init(struct dw_spi_priv *priv)
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
+static int dw_spi_of_get_clk(struct udevice *bus)
+{
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ ret = clk_enable(&clk);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ priv->bus_clk_rate = clk_get_rate(&clk);
+ if (!priv->bus_clk_rate) {
+ clk_disable(&clk);
+ return -EINVAL;
+ }
+
+ clk_free(&clk);
+
+ return 0;
+}
+#endif
+
+static int dw_spi_get_clk(struct udevice *bus)
+{
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
+ int ret;
+
+ /* Try to get clock frequency from device tree */
+ ret = dw_spi_of_get_clk(bus);
+ if (ret)
+ return ret;
+#else
+ /*
+ * Some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't implement
+ * generic clock framework and use cm_get_spi_controller_clk_hz
+ * function (defined in asm/arch/clock_manager.h) to get spi controller
+ * clock frequency.
+ */
+ priv->bus_clk_rate = cm_get_spi_controller_clk_hz();
+#endif
+
+ if (!priv->bus_clk_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
static int dw_spi_probe(struct udevice *bus)
{
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
priv->regs = plat->regs;
priv->freq = plat->frequency;
+ ret = dw_spi_get_clk(bus);
+ if (ret)
+ return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
@@ -369,7 +436,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
spi_enable_chip(priv, 0);
/* clk_div doesn't support odd number */
- clk_div = cm_get_spi_controller_clk_hz() / speed;
+ clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_writel(priv, DW_SPI_BAUDR, clk_div);
Add option to set spi controller clock frequency via device tree using standard clock bindings. Old way of setting spi controller clock frequency (via implementation of 'cm_get_spi_controller_clk_hz' function in platform specific code) remains supported for backward compatibility with targets which don't use generic clock framework. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> --- Marek, Jagan, How about this implementation? As both SOCFPGA_GEN5 and SOCFPGA_ARRIA10 don't use generic clock framework, we can determine way of clock getting based on CONFIG_IS_ENABLED(CLK) macro. So we don't need any weak functions / soc-specific ifdefs in driver / changes in SOCFPGA_* stuff. Changes v2->v3: * get rid of soc-specific ifdefs in driver. Changes v1->v2: * disable clock if we can't get the rate. * get rid of cm_get_spi_controller_clk_hz weak declaration. drivers/spi/designware_spi.c | 69 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-)