| Message ID | 20170417190034.71945-11-maxims@google.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
On 17 April 2017 at 13:00, Maxim Sloyko <maxims@google.com> wrote: > Add P-Bus Clock support to ast2500 clock driver. > This is the clock used by I2C devices. > > Signed-off-by: Maxim Sloyko <maxims@google.com> > --- > > Changes in v1: None > > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++- > drivers/clk/aspeed/clk_ast2500.c | 11 +++++++++++ > 2 files changed, 13 insertions(+), 1 deletion(-) > Reviewed-by: Simon Glass <sjg@chromium.org> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h > index 1cdd3b9198..319d75e05c 100644 > --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h > @@ -21,7 +21,8 @@ > #define SCU_MPLL_NUM_MASK 0xff > #define SCU_MPLL_POST_SHIFT 13 > #define SCU_MPLL_POST_MASK 0x3f I think it works better in general if the mask is defined as 0x3f << SCU_MPLL_POST_SHIFT. Something to think about as a possible clean-up. > - > +#define SCU_PCLK_DIV_SHIFT 23 > +#define SCU_PCLK_DIV_MASK 7 > #define SCU_HPLL_DENUM_SHIFT 0 > #define SCU_HPLL_DENUM_MASK 0x1f > #define SCU_HPLL_NUM_SHIFT 5 > diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c > index 504731271c..9e4c66ea85 100644 > --- a/drivers/clk/aspeed/clk_ast2500.c > +++ b/drivers/clk/aspeed/clk_ast2500.c > @@ -110,6 +110,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk) > rate = ast2500_get_mpll_rate(clkin, > readl(&priv->scu->m_pll_param)); > break; > + case BCLK_PCLK: > + { > + ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) > + >> SCU_PCLK_DIV_SHIFT) & > + SCU_PCLK_DIV_MASK); > + rate = ast2500_get_hpll_rate(clkin, > + readl(&priv->scu-> > + h_pll_param)); > + rate = rate / apb_div; > + } > + break; > case PCLK_UART1: > rate = ast2500_get_uart_clk_rate(priv->scu, 1); > break; > -- > 2.12.2.762.g0e3151a226-goog > Regards, Simon
On Mon, Apr 17, 2017 at 12:00:29PM -0700, maxims@google.com wrote: > Add P-Bus Clock support to ast2500 clock driver. > This is the clock used by I2C devices. > > Signed-off-by: Maxim Sloyko <maxims@google.com> > Reviewed-by: Simon Glass <sjg@chromium.org> Applied to u-boot/master, thanks!
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index 1cdd3b9198..319d75e05c 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -21,7 +21,8 @@ #define SCU_MPLL_NUM_MASK 0xff #define SCU_MPLL_POST_SHIFT 13 #define SCU_MPLL_POST_MASK 0x3f - +#define SCU_PCLK_DIV_SHIFT 23 +#define SCU_PCLK_DIV_MASK 7 #define SCU_HPLL_DENUM_SHIFT 0 #define SCU_HPLL_DENUM_MASK 0x1f #define SCU_HPLL_NUM_SHIFT 5 diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 504731271c..9e4c66ea85 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -110,6 +110,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = ast2500_get_mpll_rate(clkin, readl(&priv->scu->m_pll_param)); break; + case BCLK_PCLK: + { + ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) + >> SCU_PCLK_DIV_SHIFT) & + SCU_PCLK_DIV_MASK); + rate = ast2500_get_hpll_rate(clkin, + readl(&priv->scu-> + h_pll_param)); + rate = rate / apb_div; + } + break; case PCLK_UART1: rate = ast2500_get_uart_clk_rate(priv->scu, 1); break;
Add P-Bus Clock support to ast2500 clock driver. This is the clock used by I2C devices. Signed-off-by: Maxim Sloyko <maxims@google.com> --- Changes in v1: None arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++- drivers/clk/aspeed/clk_ast2500.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-)