diff mbox

[U-Boot,3/4] ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DT

Message ID 20160912175115.13198-3-swarren@wwwdotorg.org
State Accepted
Commit 31c1ff90e2070759dd8c35a182f96c342543dad6
Delegated to: Joe Hershberger
Headers show

Commit Message

Stephen Warren Sept. 12, 2016, 5:51 p.m. UTC 
From: Stephen Warren <swarren@nvidia.com>

Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the
Tegra186 SoC DT so that boards can make use of it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/dts/tegra186.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Simon Glass Sept. 19, 2016, 12:58 a.m. UTC | #1 
On 12 September 2016 at 11:51, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the
> Tegra186 SoC DT so that boards can make use of it.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/dts/tegra186.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Joe Hershberger Nov. 2, 2016, 8:31 p.m. UTC | #2 
On Mon, Sep 12, 2016 at 12:51 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the
> Tegra186 SoC DT so that boards can make use of it.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger Nov. 7, 2016, 5:31 p.m. UTC | #3 
Hi Stephen,

https://patchwork.ozlabs.org/patch/668912/ was applied to u-boot-net.git.

Thanks!
-Joe
diff mbox

Patch

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index f878b6532510..dd9e3b869de7 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -31,6 +31,26 @@ 
 		#interrupt-cells = <2>;
 	};
 
+	ethernet@2490000 {
+		compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
+		reg = <0x0 0x02490000 0x0 0x10000>;
+		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
+			<&bpmp TEGRA186_CLK_EQOS_AXI>,
+			<&bpmp TEGRA186_CLK_EQOS_RX>,
+			<&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
+			<&bpmp TEGRA186_CLK_EQOS_TX>;
+		clock-names = "slave_bus",
+			"master_bus",
+			"rx",
+			"ptp_ref",
+			"tx";
+		resets = <&bpmp TEGRA186_RESET_EQOS>;
+		reset-names = "eqos";
+		phy-mode = "rgmii";
+		status = "disabled";
+	};
+
 	uarta: serial@3100000 {
 		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 		reg = <0x0 0x03100000 0x0 0x10000>;