| Message ID | 20160722052550.13339-3-vigneshr@ti.com |
|---|---|
| State | Accepted |
| Commit | fee3b6af903c0e24b662694427b62658f40c7d4b |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On 22 July 2016 at 10:55, Vignesh R <vigneshr@ti.com> wrote: > As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay > for successful bulk erase) says its added to meet bulk erase timing > constraints. But bulk erase is a cmd to flash and delay in read path > does not make sense. Morever, testing on DRA74/DRA72 evm has shown that > this delay is no longer required. > > Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> > --- > > v2: no patch > > drivers/spi/ti_qspi.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c > index 56ae29a3ee7c..fa7ee229878a 100644 > --- a/drivers/spi/ti_qspi.c > +++ b/drivers/spi/ti_qspi.c > @@ -249,9 +249,6 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, > if (rxp) { > debug("rx cmd %08x dc %08x\n", > ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc); > - #ifdef CONFIG_DRA7XX > - udelay(500); > - #endif Thanks for this change. -- Jagan.
On Friday 22 July 2016 10:55 AM, Vignesh R wrote: > As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay > for successful bulk erase) says its added to meet bulk erase timing > constraints. But bulk erase is a cmd to flash and delay in read path > does not make sense. Morever, testing on DRA74/DRA72 evm has shown that > this delay is no longer required. > > Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Regards Mugunthan V N
On 22 July 2016 at 15:39, Mugunthan V N <mugunthanvnm@ti.com> wrote: > On Friday 22 July 2016 10:55 AM, Vignesh R wrote: >> As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay >> for successful bulk erase) says its added to meet bulk erase timing >> constraints. But bulk erase is a cmd to flash and delay in read path >> does not make sense. Morever, testing on DRA74/DRA72 evm has shown that >> this delay is no longer required. >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> > > Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Applied to u-boot-spi/master thanks!
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 56ae29a3ee7c..fa7ee229878a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -249,9 +249,6 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, if (rxp) { debug("rx cmd %08x dc %08x\n", ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc); - #ifdef CONFIG_DRA7XX - udelay(500); - #endif writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd); status = readl(&priv->base->status); timeout = QSPI_TIMEOUT;
As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: Vignesh R <vigneshr@ti.com> --- v2: no patch drivers/spi/ti_qspi.c | 3 --- 1 file changed, 3 deletions(-)