| Message ID | 201601210232.53143.marex@denx.de |
|---|---|
| State | Not Applicable |
| Delegated to: | Marek Vasut |
| Headers | show |
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote: > On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote: >> On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote: >>> 2016-01-17 6:49 GMT+01:00 Wills Wang <wills.wang@live.com>: >>>> On 01/17/2016 03:05 AM, Marek Vasut wrote: >>>>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: >>>>>> These series of patch add support for atheros ath79 based SOCs in >>>>>> u-boot, at the present moment it's just available for ar933x and >>>>>> qca953x chip. >>>>>> >>>>>> This patch serises is based on mips_io_v4 branch on u-boot-mips >>>>>> repository >>>>>> [1] and tested on ar933x and qca953x board. >>>>>> >>>>>> [1] >>>>>> >>>>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/m >>>>>> ips_ io_v4 >>>>> So if I didn't complain about this being sent as separate emails this >>>>> morning. >>>>> Please, do send your patches as a series, not as separate emails. >>>> How to send a patch series by patman? >>> If your git-sendmail config is correctly set up, patman automatically >>> sends the cover letter and then all patches as response to that cover >>> letter. >>> >>> You have to enable mail threading in git-sendmail. Check that with: >>> >>> $ git config --get sendemail.thread >>> >>> To enable it globally: >>> >>> $ git config --global sendemail.thread true >> Thanks, i will try it for the coming v8. > I got as far as booting my ar9330 rev 1 machine, though it did take considerably > amount of hackery. I also had to use locked cachelines for stack, because it is > far faster than using the SRAM on ar9331 . You can find my hacks in the > attachment, most of the stuff there is because arduino yun is repugnant crappy > piece of hardware and needs some extra treatment. My board is also ar9330 rev 1, but i can boot well without any change for start.s and cache, is it possible about hardware? My board work fine when i use DDR or SRAM for stack. > You should mostly care about the hacks in start.S , in particular the one > setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. > Daniel seems to have some ideas on this too I think, he helped me finding > out there's a problem. > > Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it > is clearly a dirty hack. The start.S needs to be modularized in some way for > this to be properly integrat(ed|able). > > In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, > but I suspect it makes no sense on a machine which has no running DRAM anyway, > so I removed this option. My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. I doubt whether there are same exceptions for your memory subsystem, or some DDR parameters are not for your DDR chip. > Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but > I suggest you double-check it. Did your board use DDR1? I check the original u-boot code again, this value 0xa33 is for DDR2, 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved. > Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR > running at low speed, since I am using an FPGA instead of real SPI NOR and > the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz. > > I am now looking into implementing ethernet and USB support for ar9331, did > you look into it at all or not ? I'd like to avoid duplicating efforts. At present, i have no plan to involve ethernet and USB, i want to work done first for this patch. > Best regards, > Marek Vasut
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote: > On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote: >> On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote: >>> 2016-01-17 6:49 GMT+01:00 Wills Wang <wills.wang@live.com>: >>>> On 01/17/2016 03:05 AM, Marek Vasut wrote: >>>>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: >>>>>> These series of patch add support for atheros ath79 based SOCs in >>>>>> u-boot, at the present moment it's just available for ar933x and >>>>>> qca953x chip. >>>>>> >>>>>> This patch serises is based on mips_io_v4 branch on u-boot-mips >>>>>> repository >>>>>> [1] and tested on ar933x and qca953x board. >>>>>> >>>>>> [1] >>>>>> >>>>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/m >>>>>> ips_ io_v4 >>>>> So if I didn't complain about this being sent as separate emails this >>>>> morning. >>>>> Please, do send your patches as a series, not as separate emails. >>>> How to send a patch series by patman? >>> If your git-sendmail config is correctly set up, patman automatically >>> sends the cover letter and then all patches as response to that cover >>> letter. >>> >>> You have to enable mail threading in git-sendmail. Check that with: >>> >>> $ git config --get sendemail.thread >>> >>> To enable it globally: >>> >>> $ git config --global sendemail.thread true >> Thanks, i will try it for the coming v8. > I got as far as booting my ar9330 rev 1 machine, though it did take considerably > amount of hackery. I also had to use locked cachelines for stack, because it is > far faster than using the SRAM on ar9331 . You can find my hacks in the > attachment, most of the stuff there is because arduino yun is repugnant crappy > piece of hardware and needs some extra treatment. > > You should mostly care about the hacks in start.S , in particular the one > setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. > Daniel seems to have some ideas on this too I think, he helped me finding > out there's a problem. > > Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it > is clearly a dirty hack. The start.S needs to be modularized in some way for > this to be properly integrat(ed|able). > > In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, > but I suspect it makes no sense on a machine which has no running DRAM anyway, > so I removed this option. > > Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but > I suggest you double-check it. > > Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR > running at low speed, since I am using an FPGA instead of real SPI NOR and > the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz. > > I am now looking into implementing ethernet and USB support for ar9331, did > you look into it at all or not ? I'd like to avoid duplicating efforts. -#define CONFIG_SYS_TEXT_BASE 0x9f000000 +#define CONFIG_SYS_TEXT_BASE 0xbf000000 Why need this change? > Best regards, > Marek Vasut
On Thursday, January 21, 2016 at 04:02:05 AM, Wills Wang wrote: > On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote: > > On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote: > >> On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote: > >>> 2016-01-17 6:49 GMT+01:00 Wills Wang <wills.wang@live.com>: > >>>> On 01/17/2016 03:05 AM, Marek Vasut wrote: > >>>>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: > >>>>>> These series of patch add support for atheros ath79 based SOCs in > >>>>>> u-boot, at the present moment it's just available for ar933x and > >>>>>> qca953x chip. > >>>>>> > >>>>>> This patch serises is based on mips_io_v4 branch on u-boot-mips > >>>>>> repository > >>>>>> [1] and tested on ar933x and qca953x board. > >>>>>> > >>>>>> [1] > >>>>>> > >>>>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads > >>>>>> /m ips_ io_v4 > >>>>> > >>>>> So if I didn't complain about this being sent as separate emails this > >>>>> morning. > >>>>> Please, do send your patches as a series, not as separate emails. > >>>> > >>>> How to send a patch series by patman? > >>> > >>> If your git-sendmail config is correctly set up, patman automatically > >>> sends the cover letter and then all patches as response to that cover > >>> letter. > >>> > >>> You have to enable mail threading in git-sendmail. Check that with: > >>> > >>> $ git config --get sendemail.thread > >>> > >>> To enable it globally: > >>> > >>> $ git config --global sendemail.thread true > >> > >> Thanks, i will try it for the coming v8. > > > > I got as far as booting my ar9330 rev 1 machine, though it did take > > considerably amount of hackery. I also had to use locked cachelines for > > stack, because it is far faster than using the SRAM on ar9331 . You can > > find my hacks in the attachment, most of the stuff there is because > > arduino yun is repugnant crappy piece of hardware and needs some extra > > treatment. > > > > You should mostly care about the hacks in start.S , in particular the one > > setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc > > core. Daniel seems to have some ideas on this too I think, he helped me > > finding out there's a problem. > > > > Also, mips_cache_lock_24k does the job for locking the cachelines, but > > (!) it is clearly a dirty hack. The start.S needs to be modularized in > > some way for this to be properly integrat(ed|able). > > > > In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No > > idea why, but I suspect it makes no sense on a machine which has no > > running DRAM anyway, so I removed this option. > > > > Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, > > but I suggest you double-check it. > > > > Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR > > running at low speed, since I am using an FPGA instead of real SPI NOR > > and the FPGA implementation of the SPI NOR emulator cannot run at tens > > of MHz. > > > > I am now looking into implementing ethernet and USB support for ar9331, > > did you look into it at all or not ? I'd like to avoid duplicating > > efforts. > > -#define CONFIG_SYS_TEXT_BASE 0x9f000000 > +#define CONFIG_SYS_TEXT_BASE 0xbf000000 > > Why need this change? I believe this has no impact, it just prevents code from being cachable which is convenient for me. You can ignore it.
On Thursday, January 21, 2016 at 03:58:44 AM, Wills Wang wrote: > On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote: > > On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote: > >> On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote: > >>> 2016-01-17 6:49 GMT+01:00 Wills Wang <wills.wang@live.com>: > >>>> On 01/17/2016 03:05 AM, Marek Vasut wrote: > >>>>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: > >>>>>> These series of patch add support for atheros ath79 based SOCs in > >>>>>> u-boot, at the present moment it's just available for ar933x and > >>>>>> qca953x chip. > >>>>>> > >>>>>> This patch serises is based on mips_io_v4 branch on u-boot-mips > >>>>>> repository > >>>>>> [1] and tested on ar933x and qca953x board. > >>>>>> > >>>>>> [1] > >>>>>> > >>>>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads > >>>>>> /m ips_ io_v4 > >>>>> > >>>>> So if I didn't complain about this being sent as separate emails this > >>>>> morning. > >>>>> Please, do send your patches as a series, not as separate emails. > >>>> > >>>> How to send a patch series by patman? > >>> > >>> If your git-sendmail config is correctly set up, patman automatically > >>> sends the cover letter and then all patches as response to that cover > >>> letter. > >>> > >>> You have to enable mail threading in git-sendmail. Check that with: > >>> > >>> $ git config --get sendemail.thread > >>> > >>> To enable it globally: > >>> > >>> $ git config --global sendemail.thread true > >> > >> Thanks, i will try it for the coming v8. > > > > I got as far as booting my ar9330 rev 1 machine, though it did take > > considerably amount of hackery. I also had to use locked cachelines for > > stack, because it is far faster than using the SRAM on ar9331 . You can > > find my hacks in the attachment, most of the stuff there is because > > arduino yun is repugnant crappy piece of hardware and needs some extra > > treatment. > > My board is also ar9330 rev 1, but i can boot well without any change for > start.s and cache, is it possible about hardware? No clue. > My board work fine when i use DDR or SRAM for stack. I remember you weren't able to boot if you used SRAM for stack. Did something change ? > > You should mostly care about the hacks in start.S , in particular the one > > setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc > > core. Daniel seems to have some ideas on this too I think, he helped me > > finding out there's a problem. > > > > Also, mips_cache_lock_24k does the job for locking the cachelines, but > > (!) it is clearly a dirty hack. The start.S needs to be modularized in > > some way for this to be properly integrat(ed|able). > > > > In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No > > idea why, but I suspect it makes no sense on a machine which has no > > running DRAM anyway, so I removed this option. > > My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. > I doubt whether there are same exceptions for your memory subsystem, or > some DDR parameters are not for your DDR chip. DDR is not started at the point where INIT_RAM_LOAD comes into play, so it has nothing to do with it. Instead, refilling the cache from DDR makes no sense if DDR is not running, therefore this should be disabled to make sure we don't run into problems. > > Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, > > but I suggest you double-check it. > > Did your board use DDR1? DDR2 > I check the original u-boot code again, this value 0xa33 is for DDR2, > 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved. That's correct, so I suspect there's something swapped somewhere, since my register ends up configured with 0x33 and not 0xa33 . That's why I hacked this change for now. > > Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR > > running at low speed, since I am using an FPGA instead of real SPI NOR > > and the FPGA implementation of the SPI NOR emulator cannot run at tens > > of MHz. > > > > I am now looking into implementing ethernet and USB support for ar9331, > > did you look into it at all or not ? I'd like to avoid duplicating > > efforts. > > At present, i have no plan to involve ethernet and USB, i want to work > done first for this patch. OK, I am looking into the ethernet part now, no luck so far. I cannot even read the PHY ID yet, probably missing some register bit somewhere.
On Thursday, January 21, 2016 01:35 PM, Marek Vasut wrote: > On Thursday, January 21, 2016 at 03:58:44 AM, Wills Wang wrote: >> On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote: >>> On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote: >>>> On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote: >>>>> 2016-01-17 6:49 GMT+01:00 Wills Wang <wills.wang@live.com>: >>>>>> On 01/17/2016 03:05 AM, Marek Vasut wrote: >>>>>>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: >>>>>>>> These series of patch add support for atheros ath79 based SOCs in >>>>>>>> u-boot, at the present moment it's just available for ar933x and >>>>>>>> qca953x chip. >>>>>>>> >>>>>>>> This patch serises is based on mips_io_v4 branch on u-boot-mips >>>>>>>> repository >>>>>>>> [1] and tested on ar933x and qca953x board. >>>>>>>> >>>>>>>> [1] >>>>>>>> >>>>>>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads >>>>>>>> /m ips_ io_v4 >>>>>>> So if I didn't complain about this being sent as separate emails this >>>>>>> morning. >>>>>>> Please, do send your patches as a series, not as separate emails. >>>>>> How to send a patch series by patman? >>>>> If your git-sendmail config is correctly set up, patman automatically >>>>> sends the cover letter and then all patches as response to that cover >>>>> letter. >>>>> >>>>> You have to enable mail threading in git-sendmail. Check that with: >>>>> >>>>> $ git config --get sendemail.thread >>>>> >>>>> To enable it globally: >>>>> >>>>> $ git config --global sendemail.thread true >>>> Thanks, i will try it for the coming v8. >>> I got as far as booting my ar9330 rev 1 machine, though it did take >>> considerably amount of hackery. I also had to use locked cachelines for >>> stack, because it is far faster than using the SRAM on ar9331 . You can >>> find my hacks in the attachment, most of the stuff there is because >>> arduino yun is repugnant crappy piece of hardware and needs some extra >>> treatment. >> My board is also ar9330 rev 1, but i can boot well without any change for >> start.s and cache, is it possible about hardware? > No clue. > >> My board work fine when i use DDR or SRAM for stack. > I remember you weren't able to boot if you used SRAM for stack. > Did something change ? What i mean is that my board can't boot if drop the whole lowlevel_init.S when use SRAM for stack. we need lowlevel_init.S to handle RTC, PLL and some chip issues. >>> You should mostly care about the hacks in start.S , in particular the one >>> setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc >>> core. Daniel seems to have some ideas on this too I think, he helped me >>> finding out there's a problem. >>> >>> Also, mips_cache_lock_24k does the job for locking the cachelines, but >>> (!) it is clearly a dirty hack. The start.S needs to be modularized in >>> some way for this to be properly integrat(ed|able). >>> >>> In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No >>> idea why, but I suspect it makes no sense on a machine which has no >>> running DRAM anyway, so I removed this option. >> My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. >> I doubt whether there are same exceptions for your memory subsystem, or >> some DDR parameters are not for your DDR chip. > DDR is not started at the point where INIT_RAM_LOAD comes into play, so > it has nothing to do with it. Instead, refilling the cache from DDR makes > no sense if DDR is not running, therefore this should be disabled to make > sure we don't run into problems. > >>> Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, >>> but I suggest you double-check it. >> Did your board use DDR1? > DDR2 > >> I check the original u-boot code again, this value 0xa33 is for DDR2, >> 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved. > That's correct, so I suspect there's something swapped somewhere, since my > register ends up configured with 0x33 and not 0xa33 . That's why I hacked > this change for now. > >>> Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR >>> running at low speed, since I am using an FPGA instead of real SPI NOR >>> and the FPGA implementation of the SPI NOR emulator cannot run at tens >>> of MHz. >>> >>> I am now looking into implementing ethernet and USB support for ar9331, >>> did you look into it at all or not ? I'd like to avoid duplicating >>> efforts. >> At present, i have no plan to involve ethernet and USB, i want to work >> done first for this patch. > OK, I am looking into the ethernet part now, no luck so far. I cannot even > read the PHY ID yet, probably missing some register bit somewhere.
On Thursday, January 21, 2016 at 10:31:50 AM, Wills Wang wrote: > On Thursday, January 21, 2016 01:35 PM, Marek Vasut wrote: > > On Thursday, January 21, 2016 at 03:58:44 AM, Wills Wang wrote: > >> On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote: > >>> On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote: > >>>> On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote: > >>>>> 2016-01-17 6:49 GMT+01:00 Wills Wang <wills.wang@live.com>: > >>>>>> On 01/17/2016 03:05 AM, Marek Vasut wrote: > >>>>>>> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: > >>>>>>>> These series of patch add support for atheros ath79 based SOCs in > >>>>>>>> u-boot, at the present moment it's just available for ar933x and > >>>>>>>> qca953x chip. > >>>>>>>> > >>>>>>>> This patch serises is based on mips_io_v4 branch on u-boot-mips > >>>>>>>> repository > >>>>>>>> [1] and tested on ar933x and qca953x board. > >>>>>>>> > >>>>>>>> [1] > >>>>>>>> > >>>>>>>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/hea > >>>>>>>> ds /m ips_ io_v4 > >>>>>>> > >>>>>>> So if I didn't complain about this being sent as separate emails > >>>>>>> this morning. > >>>>>>> Please, do send your patches as a series, not as separate emails. > >>>>>> > >>>>>> How to send a patch series by patman? > >>>>> > >>>>> If your git-sendmail config is correctly set up, patman automatically > >>>>> sends the cover letter and then all patches as response to that cover > >>>>> letter. > >>>>> > >>>>> You have to enable mail threading in git-sendmail. Check that with: > >>>>> > >>>>> $ git config --get sendemail.thread > >>>>> > >>>>> To enable it globally: > >>>>> > >>>>> $ git config --global sendemail.thread true > >>>> > >>>> Thanks, i will try it for the coming v8. > >>> > >>> I got as far as booting my ar9330 rev 1 machine, though it did take > >>> considerably amount of hackery. I also had to use locked cachelines for > >>> stack, because it is far faster than using the SRAM on ar9331 . You can > >>> find my hacks in the attachment, most of the stuff there is because > >>> arduino yun is repugnant crappy piece of hardware and needs some extra > >>> treatment. > >> > >> My board is also ar9330 rev 1, but i can boot well without any change > >> for start.s and cache, is it possible about hardware? > > > > No clue. > > > >> My board work fine when i use DDR or SRAM for stack. > > > > I remember you weren't able to boot if you used SRAM for stack. > > Did something change ? > > What i mean is that my board can't boot if drop the whole lowlevel_init.S > when use SRAM for stack. we need lowlevel_init.S to handle RTC, PLL and > some chip issues. Aha , okay. That's unfortunate indeed. > >>> You should mostly care about the hacks in start.S , in particular the > >>> one setting bit 3 in CP0 in setup_c0_status seems important on mips > >>> 24kc core. Daniel seems to have some ideas on this too I think, he > >>> helped me finding out there's a problem. > >>> > >>> Also, mips_cache_lock_24k does the job for locking the cachelines, but > >>> (!) it is clearly a dirty hack. The start.S needs to be modularized in > >>> some way for this to be properly integrat(ed|able). > >>> > >>> In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No > >>> idea why, but I suspect it makes no sense on a machine which has no > >>> running DRAM anyway, so I removed this option. > >> > >> My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. > >> I doubt whether there are same exceptions for your memory subsystem, or > >> some DDR parameters are not for your DDR chip. > > > > DDR is not started at the point where INIT_RAM_LOAD comes into play, so > > it has nothing to do with it. Instead, refilling the cache from DDR makes > > no sense if DDR is not running, therefore this should be disabled to make > > sure we don't run into problems. > > > >>> Change to ddr.c seems correct, the values for DDR1 and DDR2 were > >>> swapped, but I suggest you double-check it. > >> > >> Did your board use DDR1? > > > > DDR2 > > > >> I check the original u-boot code again, this value 0xa33 is for DDR2, > >> 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved. > > > > That's correct, so I suspect there's something swapped somewhere, since > > my register ends up configured with 0x33 and not 0xa33 . That's why I > > hacked this change for now. > > > >>> Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI > >>> NOR running at low speed, since I am using an FPGA instead of real SPI > >>> NOR and the FPGA implementation of the SPI NOR emulator cannot run at > >>> tens of MHz. > >>> > >>> I am now looking into implementing ethernet and USB support for ar9331, > >>> did you look into it at all or not ? I'd like to avoid duplicating > >>> efforts. > >> > >> At present, i have no plan to involve ethernet and USB, i want to work > >> done first for this patch. > > > > OK, I am looking into the ethernet part now, no luck so far. I cannot > > even read the PHY ID yet, probably missing some register bit somewhere.
From 16aa0d1c99f09149fa567ff4b15c46f61fe8e550 Mon Sep 17 00:00:00 2001 From: Marek Vasut <marex@denx.de> Date: Sat, 16 Jan 2016 06:27:02 +0100 Subject: [PATCH] mips experiments Signed-off-by: Marek Vasut <marex@denx.de> --- arch/mips/cpu/start.S | 53 +++++++++++++++++++++++++++++ arch/mips/dts/ap121.dts | 1 + arch/mips/mach-ath79/Kconfig | 2 -- arch/mips/mach-ath79/ar933x/ddr.c | 4 +-- arch/mips/mach-ath79/ar933x/lowlevel_init.S | 28 ++++++++++++++- arch/mips/mach-ath79/cpu.c | 4 +-- arch/mips/mach-ath79/reset.c | 6 ++-- board/ath79/ap121/ap121.c | 36 +++++++++++--------- common/board_r.c | 2 +- configs/ap121_defconfig | 6 +--- drivers/serial/serial_ar933x.c | 5 ++- include/configs/ap121.h | 26 +++++--------- 12 files changed, 121 insertions(+), 52 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index e95cdca..7c124af 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -12,6 +12,24 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> +.macro LED led + li t0, 0x18040000 + + /* OE */ + li t1, 0x600cff + sw t1, (t0) + + li t1, 0x3 + li t2, \led + + sw t1, 0x10(t0) + sw t2, 0xc(t0) +/* + nop + b . + nop*/ +.endm + #ifndef CONFIG_SYS_MIPS_CACHE_MODE #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif @@ -48,6 +66,7 @@ mfc0 t0, CP0_STATUS or t0, ST0_CU0 | \set | 0x1f | \clr xor t0, 0x1f | \clr + or t0, 0x4 mtc0 t0, CP0_STATUS .set noreorder sll zero, 3 # ehb @@ -144,6 +163,11 @@ reset: 1: PTR_L gp, 0(ra) + li t0, 0x1f000000 + li t1, 0x20 + sw t1, 0x4(t0) + + #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* Initialize any external memory */ PTR_LA t9, lowlevel_init @@ -160,6 +184,10 @@ reset: mtc0 t0, CP0_CONFIG #endif + PTR_LA t9, mips_cache_lock_24k + jalr t9 + nop + /* Set up temporary stack */ PTR_LI t0, -16 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR @@ -174,6 +202,7 @@ reset: #endif move fp, sp + /* Clear gd */ move t0, k0 1: @@ -186,6 +215,8 @@ reset: sw sp, 0(t0) #endif + move a0, zero + PTR_LA t9, board_init_f jr t9 move ra, zero @@ -316,3 +347,25 @@ in_ram: move ra, zero END(relocate_code) + + +LEAF(mips_cache_lock_24k) + li t0, CONFIG_SYS_INIT_RAM_SIZE + li t1, CONFIG_SYS_CACHELINE_SIZE + li t2, 0x80000000 /* CKSEG0 */ + addu t3, t0, t2 + mtc0 zero, CP0_TAGLO +cache_loop_lock: + li t5, 0xfffff000 + and t4, t2, t5 + ori t4, t4, (1 << 7) + mtc0 t4, CP0_TAGLO + + cache /*Index_Load_Tag_D*/ 0x5, 0(t2) + cache 0x1d, 0(t2) + addu t2, t1 + bne t2, t3, cache_loop_lock + nop + jr ra + nop +END(mips_cache_lock_24k) diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts index f7c3a1a..d103457 100644 --- a/arch/mips/dts/ap121.dts +++ b/arch/mips/dts/ap121.dts @@ -21,6 +21,7 @@ &uart0 { status = "okay"; + u-boot,dm-pre-reloc; }; &spi0 { diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index f61efd2..95f7de9 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -12,7 +12,6 @@ config SOC_AR933X select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 - select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_24KC help This supports QCA/Atheros ar933x family SOCs. @@ -22,7 +21,6 @@ config SOC_QCA953X select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 - select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_24KC help This supports QCA/Atheros qca953x family SOCs. diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c index 675d922..63785c4 100644 --- a/arch/mips/mach-ath79/ar933x/ddr.c +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -98,8 +98,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DDR2_EXT_MODE_OCD_VAL 0x382 #define DDR1_MODE_DLL_VAL 0x133 #define DDR2_MODE_DLL_VAL 0x100 -#define DDR1_MODE_VAL 0x33 -#define DDR2_MODE_VAL 0xa33 +#define DDR2_MODE_VAL 0x33 +#define DDR1_MODE_VAL 0xa33 #define DDR_TAP_VAL0 0x08 #define DDR_TAP_VAL1 0x09 diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S index ac4c364..4bee426 100644 --- a/arch/mips/mach-ath79/ar933x/lowlevel_init.S +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -28,6 +28,31 @@ ((0x3 & (ddrdiv - 1)) << 10) | \ ((0x3 & (ahbdiv - 1)) << 15) ) +.macro LED led + li t0, 0x00000018 + sll t0, t0, 8 + ori t0, t0, 0x04 + sll t0, t0, 16 + + /* OE */ + li t1, 0x60 + sll t1, t1, 8 + ori t1, t1, 0x0c + sll t1, t1, 8 + ori t1, t1, 0xff + sw t1, (t0) + + li t1, 0x3 + li t2, \led + + sw t1, 0x10(t0) + sw t2, 0xc(t0) + + nop + b . + nop +.endm + /* * PLL_CPU_CONFIG_VAL * @@ -270,7 +295,8 @@ LEAF(lowlevel_init) /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ li t0, KSEG1ADDR(AR71XX_PLL_BASE) - li t1, PLL_CLK_CONTROL_VAL + /* Keep AHB at /4 */ + li t1, SET_BIT(SET_BIT(PLL_CLK_CONTROL_VAL, 15), 16) sw t1, AR933X_PLL_CLK_CTRL_REG(t0) nop diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c index 2952679..140c65c 100644 --- a/arch/mips/mach-ath79/cpu.c +++ b/arch/mips/mach-ath79/cpu.c @@ -9,8 +9,8 @@ #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> -#include <asm/arch/ath79.h> -#include <asm/arch/ar71xx_regs.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> struct ath79_soc_desc { enum ath79_soc_type soc; diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index 410b900..186cdc5 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -9,12 +9,12 @@ #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> -#include <asm/arch/ath79.h> +#include <mach/ath79.h> #include <mach/ar71xx_regs.h> void _machine_restart(void) { - const void __iomem *base; + void __iomem *base; u32 val, reg = 0; base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, @@ -50,7 +50,7 @@ void _machine_restart(void) u32 get_bootstrap(void) { - const void __iomem *base; + void __iomem *base; u32 reg = 0; base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, diff --git a/board/ath79/ap121/ap121.c b/board/ath79/ap121/ap121.c index 901b09a..4ed9e21 100644 --- a/board/ath79/ap121/ap121.c +++ b/board/ath79/ap121/ap121.c @@ -15,34 +15,36 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { void __iomem *regs; - u32 val; regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, MAP_NOCACHE); - /* - * GPIO9 as input, GPIO10 as output - */ - val = readl(regs + AR71XX_GPIO_REG_OE); - val &= ~AR933X_GPIO(9); - val |= AR933X_GPIO(10); - writel(val, regs + AR71XX_GPIO_REG_OE); - - /* - * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO - */ - val = readl(regs + AR71XX_GPIO_REG_FUNC); - val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; - writel(val, regs + AR71XX_GPIO_REG_FUNC); + writel(AR933X_GPIO(22) | AR933X_GPIO(21) | AR933X_GPIO(11) | + AR933X_GPIO(10) | AR933X_GPIO(7) | AR933X_GPIO(6) | + AR933X_GPIO(5) | AR933X_GPIO(4) | AR933X_GPIO(3) | + AR933X_GPIO(2) | AR933X_GPIO(1) | AR933X_GPIO(0), + regs + AR71XX_GPIO_REG_OE); + + writel(AR933X_GPIO(18) | AR933X_GPIO(17) | AR933X_GPIO(10) | + AR933X_GPIO(2), regs + AR71XX_GPIO_REG_OUT); + + writel(AR933X_GPIO_FUNC_SPI_EN | + AR933X_GPIO_FUNC_RES_TRUE | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_UART_EN, + regs + AR71XX_GPIO_REG_FUNC); #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif ddr_init(); + return 0; } -#endif diff --git a/common/board_r.c b/common/board_r.c index 75ee43e..1144292 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -182,7 +182,7 @@ static int initr_reloc_global_data(void) static int initr_serial(void) { - serial_initialize(); + //serial_initialize(); return 0; } diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index d928ba8..a132b7a 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -9,7 +9,7 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_DEFAULT_DEVICE_TREE="ap121" CONFIG_SYS_PROMPT="ap121 # " -# CONFIG_CMD_BDI is not set +CONFIG_CMD_BDI=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set @@ -36,7 +36,3 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_MTD=y -CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_AR933X=y -CONFIG_DEBUG_UART_BASE=0x18020000 -CONFIG_DEBUG_UART_CLOCK=25000000 diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index 38d34c2..81aaf8a 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -75,6 +75,10 @@ static void ar933x_serial_get_scale_step(u32 clk, u32 baud, u32 tscale, baudrate; long min_diff; + *scale = 0x17; + *step = 0x7ea0; + return; + *scale = 0; *step = 0; @@ -138,7 +142,6 @@ static int ar933x_serial_getc(struct udevice *dev) if (!(data & AR933X_UART_DATA_RX_CSR)) return -EAGAIN; - data = ar933x_serial_read(dev, AR933X_UART_DATA_REG); ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR, AR933X_UART_DATA_REG); return data & AR933X_UART_DATA_TX_RX_MASK; diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 04a80e7..f1d14fa 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -1,7 +1,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_TEXT_BASE 0x9f000000 +#define CONFIG_SYS_TEXT_BASE 0xbf000000 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -26,7 +26,7 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) @@ -39,28 +39,16 @@ #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock2 " \ "rootfstype=squashfs" -#define CONFIG_BOOTCOMMAND "sf probe;" \ - "mtdparts default;" \ - "bootm 0x9f300000" -#define CONFIG_LZMA +#define CONFIG_BOOTCOMMAND "echo OK" #define CONFIG_OF_LIBFDT -#define MTDIDS_DEFAULT "nor0=spi-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ - "256k(u-boot),64k(u-boot-env)," \ - "2752k(rootfs),896k(uImage)," \ - "64k(NVRAM),64k(ART)" - -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x1000 /* * Command */ -#define CONFIG_CMD_MTDPARTS /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 256 @@ -78,4 +66,6 @@ #define CONFIG_SYS_MEMTEST_END 0x83f00000 #define CONFIG_CMD_MEMTEST +#define CONFIG_USE_PRIVATE_LIBGCC + #endif /* __CONFIG_H */ -- 2.1.4