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[1/2] mmc: fsl_esdhc_imx: fix the mask for tuning start point

Message ID 1592825884-22136-1-git-send-email-haibo.chen@nxp.com
State Accepted
Commit 135c10a7834aa7e0f26f52e5173925e695cba48f
Delegated to: Peng Fan
Headers show
Series [1/2] mmc: fsl_esdhc_imx: fix the mask for tuning start point | expand

Commit Message

Bough Chen June 22, 2020, 11:38 a.m. UTC 
From: Haibo Chen <haibo.chen@nxp.com>

According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
TUNING_START_TAP, bit[7] of this register is to disable the command
CRC check for standard tuning. So fix it here.

Fixes: fa33d207494c ("mmc: split fsl_esdhc driver for i.MX")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 include/fsl_esdhc_imx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index 33c6d52bfe..220a76b9ee 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -203,7 +203,7 @@ 
 #define ESDHC_STD_TUNING_EN             BIT(24)
 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 #define ESDHC_TUNING_START_TAP_DEFAULT	0x1
-#define ESDHC_TUNING_START_TAP_MASK	0xff
+#define ESDHC_TUNING_START_TAP_MASK	0x7f
 #define ESDHC_TUNING_STEP_MASK		0x00070000
 #define ESDHC_TUNING_STEP_SHIFT		16