| Message ID | 1579810566-11675-8-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Fix currently available support for flash on HiFive Unleashed | expand |
On 24/01/20 1:46 am, Sagar Shrikant Kadam wrote: > This patch adds a workaround to change the read/write opcodes > from QUAD to single bit mode. Idea here is to enable usage of > spi-flash on the board. > > TODO: > -Enable QUAD mode for spi-flash on HiFive Unleashed A00 board. > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > --- > drivers/mtd/spi/spi-nor-core.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > index c55116f..35d7772 100644 > --- a/drivers/mtd/spi/spi-nor-core.c > +++ b/drivers/mtd/spi/spi-nor-core.c > @@ -295,7 +295,19 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, > nor->erase_opcode = SPINOR_OP_SE; > nor->mtd.erasesize = info->sector_size; > break; > - > +#ifdef CONFIG_TARGET_SIFIVE_FU540 > + /* > + * This flash device does support QUAD bit mode. But > + * with tx-rx width specified to 4 bit mode in dt the spi > + * driver is unable to access flash device. TODO: Once basic > + * operational support is moved to mainline remove this workaround. > + */ > + case SNOR_MFR_ISSI: > + nor->read_opcode = SPINOR_OP_READ_FAST; > + nor->program_opcode = SPINOR_OP_PP; > + break; > +#endif > + default: NACK. Sorry, no Target specific #if'dery hacks in spi-nor-core please. Either debug and fix the issue or set tx-rx width to values that actually work in the mainline. You can switch tx-rx width to 4 when TODO is actually done. > break; > } > > @@ -2636,6 +2648,7 @@ int spi_nor_scan(struct spi_nor *nor) > /* enable 4-byte addressing if the device exceeds 16MiB */ > nor->addr_width = 4; > if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || > + JEDEC_MFR(info) == SNOR_MFR_ISSI || > info->flags & SPI_NOR_4B_OPCODES) > spi_nor_set_4byte_opcodes(nor, info); > #else >
Hello Vignesh, > -----Original Message----- > From: Vignesh Raghavendra <vigneshr@ti.com> > Sent: Friday, January 24, 2020 10:25 AM > To: Sagar Kadam <sagar.kadam@sifive.com>; u-boot@lists.denx.de > Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; > anup.patel@wdc.com; ick@andestech.com; atish.patra@wdc.com; > jagan@amarulasolutions.com > Subject: Re: [U-Boot Patch v1 7/7] fu540: spi-nor: modify the flash read and > program opcodes > > > > On 24/01/20 1:46 am, Sagar Shrikant Kadam wrote: > > This patch adds a workaround to change the read/write opcodes > > from QUAD to single bit mode. Idea here is to enable usage of > > spi-flash on the board. > > > > TODO: > > -Enable QUAD mode for spi-flash on HiFive Unleashed A00 board. > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > > --- > > drivers/mtd/spi/spi-nor-core.c | 15 ++++++++++++++- > > 1 file changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > > index c55116f..35d7772 100644 > > --- a/drivers/mtd/spi/spi-nor-core.c > > +++ b/drivers/mtd/spi/spi-nor-core.c > > @@ -295,7 +295,19 @@ static void spi_nor_set_4byte_opcodes(struct > spi_nor *nor, > > nor->erase_opcode = SPINOR_OP_SE; > > nor->mtd.erasesize = info->sector_size; > > break; > > - > > +#ifdef CONFIG_TARGET_SIFIVE_FU540 > > + /* > > + * This flash device does support QUAD bit mode. But > > + * with tx-rx width specified to 4 bit mode in dt the spi > > + * driver is unable to access flash device. TODO: Once basic > > + * operational support is moved to mainline remove this > workaround. > > + */ > > + case SNOR_MFR_ISSI: > > + nor->read_opcode = SPINOR_OP_READ_FAST; > > + nor->program_opcode = SPINOR_OP_PP; > > + break; > > +#endif > > + default: > > NACK. > > Sorry, no Target specific #if'dery hacks in spi-nor-core please. Either > debug and fix the issue or set tx-rx width to values that actually work > in the mainline. You can switch tx-rx width to 4 when TODO is actually done. > Ok, no problem. So till TODO is actually done, I will modify the existing hifive-unleashed-a00.dts present in U-Boot and submit a V2 without these work-arounds. Thanks & BR, -Sagar > > break; > > } > > > > @@ -2636,6 +2648,7 @@ int spi_nor_scan(struct spi_nor *nor) > > /* enable 4-byte addressing if the device exceeds 16MiB */ > > nor->addr_width = 4; > > if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || > > + JEDEC_MFR(info) == SNOR_MFR_ISSI || > > info->flags & SPI_NOR_4B_OPCODES) > > spi_nor_set_4byte_opcodes(nor, info); > > #else > > > > -- > Regards > Vignesh
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index c55116f..35d7772 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -295,7 +295,19 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, nor->erase_opcode = SPINOR_OP_SE; nor->mtd.erasesize = info->sector_size; break; - +#ifdef CONFIG_TARGET_SIFIVE_FU540 + /* + * This flash device does support QUAD bit mode. But + * with tx-rx width specified to 4 bit mode in dt the spi + * driver is unable to access flash device. TODO: Once basic + * operational support is moved to mainline remove this workaround. + */ + case SNOR_MFR_ISSI: + nor->read_opcode = SPINOR_OP_READ_FAST; + nor->program_opcode = SPINOR_OP_PP; + break; +#endif + default: break; } @@ -2636,6 +2648,7 @@ int spi_nor_scan(struct spi_nor *nor) /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || + JEDEC_MFR(info) == SNOR_MFR_ISSI || info->flags & SPI_NOR_4B_OPCODES) spi_nor_set_4byte_opcodes(nor, info); #else
This patch adds a workaround to change the read/write opcodes from QUAD to single bit mode. Idea here is to enable usage of spi-flash on the board. TODO: -Enable QUAD mode for spi-flash on HiFive Unleashed A00 board. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> --- drivers/mtd/spi/spi-nor-core.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)