diff mbox series

[U-Boot] clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

Message ID 1516381360-10658-1-git-send-email-patrice.chotard@st.com
State Accepted
Commit 990dba649852d79a3ac5f9540a713f6207cf7ea8
Delegated to: Tom Rini
Headers show
Series [U-Boot] clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value | expand

Commit Message

Patrice CHOTARD Jan. 19, 2018, 5:02 p.m. UTC 
From: Patrice Chotard <patrice.chotard@st.com>

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
  00: PLLSAIP = 2
  01: PLLSAIP = 4
  10: PLLSAIP = 6
  11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/clk/clk_stm32f.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Tom Rini Jan. 28, 2018, 6:53 p.m. UTC | #1 
On Fri, Jan 19, 2018 at 06:02:40PM +0100, patrice.chotard@st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
> register, available combination are :
>   00: PLLSAIP = 2
>   01: PLLSAIP = 4
>   10: PLLSAIP = 6
>   11: PLLSAIP = 8
> 
> Previously, the divider value was incorrectly set to 6.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 63116e0..51fea8d 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -59,7 +59,7 @@ 
 #define RCC_PLLCFGR_PLLSAIP_MASK	GENMASK(17, 16)
 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT	6
 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT	16
-#define RCC_PLLSAICFGR_PLLSAIP_4	BIT(17)
+#define RCC_PLLSAICFGR_PLLSAIP_4	BIT(16)
 #define RCC_PLLSAICFGR_PLLSAIQ_4	BIT(26)
 #define RCC_PLLSAICFGR_PLLSAIR_2	BIT(29)