diff mbox series

[U-Boot,1/3] armv8: fsl-layerscape: SPL size reduction

Message ID 1503990107-28658-1-git-send-email-sumit.garg@nxp.com
State Superseded
Delegated to: York Sun
Headers show
Series [U-Boot,1/3] armv8: fsl-layerscape: SPL size reduction | expand

Commit Message

Sumit Garg Aug. 29, 2017, 7:01 a.m. UTC 
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Compile-off mp.c and libfdt.c in case of SPL build.
2. Keep MMU and DCACHE specific variable and functions under
   CONFIG_SYS_DCACHE_OFF macro.
3. Compile-off IFC specific funtion call "init_early_memctl_regs"
   in case of SPL build.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
---

Dependent on ls1088 base SD boot target. Also dependent on ls1088
QPSI secure boot target.

 arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c    | 6 ++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c    | 2 ++
 3 files changed, 10 insertions(+)

Comments

York Sun Sept. 14, 2017, 8:38 p.m. UTC | #1 
On 08/29/2017 12:01 AM, Sumit Garg wrote:
> Using changes in this patch we were able to reduce approx 4k
> size of u-boot-spl.bin image. Following is breif description of
> changes to reduce SPL size:
> 1. Compile-off mp.c and libfdt.c in case of SPL build.
> 2. Keep MMU and DCACHE specific variable and functions under
>     CONFIG_SYS_DCACHE_OFF macro.
> 3. Compile-off IFC specific funtion call "init_early_memctl_regs"
>     in case of SPL build.
> 
> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
> ---
> 
> Dependent on ls1088 base SD boot target. Also dependent on ls1088
> QPSI secure boot target.

I don't agree D-cache should be off for SPL boot. Please find other way 
to reduce SPL image size.

York
Sumit Garg Oct. 3, 2017, 10:51 a.m. UTC | #2 
> -----Original Message-----
> From: York Sun
> Sent: Friday, September 15, 2017 2:08 AM
> To: Sumit Garg <sumit.garg@nxp.com>; u-boot@lists.denx.de
> Cc: Ruchika Gupta <ruchika.gupta@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>
> Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
> 
> On 08/29/2017 12:01 AM, Sumit Garg wrote:
> > Using changes in this patch we were able to reduce approx 4k size of
> > u-boot-spl.bin image. Following is breif description of changes to
> > reduce SPL size:
> > 1. Compile-off mp.c and libfdt.c in case of SPL build.
> > 2. Keep MMU and DCACHE specific variable and functions under
> >     CONFIG_SYS_DCACHE_OFF macro.
> > 3. Compile-off IFC specific funtion call "init_early_memctl_regs"
> >     in case of SPL build.
> >
> > Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
> > ---
> >
> > Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI
> > secure boot target.
> 
> I don't agree D-cache should be off for SPL boot. Please find other way to
> reduce SPL image size.
> 
> York
 
Sure, let me use GCC 6.2 to reduce SPL image size in upstream rather than compiling-off
D-cache code.

But I still don't see ls1088ardb sd boot support in upstream.

Ashish,

By when can I expect ls1088ardb sd boot support in upstream?

Sumit
York Sun Oct. 4, 2017, 6:41 p.m. UTC | #3 
On 10/03/2017 03:51 AM, Sumit Garg wrote:
>> -----Original Message-----
>> From: York Sun
>> Sent: Friday, September 15, 2017 2:08 AM
>> To: Sumit Garg <sumit.garg@nxp.com>; u-boot@lists.denx.de
>> Cc: Ruchika Gupta <ruchika.gupta@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>
>> Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
>>
>> On 08/29/2017 12:01 AM, Sumit Garg wrote:
>>> Using changes in this patch we were able to reduce approx 4k size of
>>> u-boot-spl.bin image. Following is breif description of changes to
>>> reduce SPL size:
>>> 1. Compile-off mp.c and libfdt.c in case of SPL build.
>>> 2. Keep MMU and DCACHE specific variable and functions under
>>>     CONFIG_SYS_DCACHE_OFF macro.
>>> 3. Compile-off IFC specific funtion call "init_early_memctl_regs"
>>>     in case of SPL build.
>>>
>>> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
>>> ---
>>>
>>> Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI
>>> secure boot target.
>>
>> I don't agree D-cache should be off for SPL boot. Please find other way to
>> reduce SPL image size.
>>
>> York
>  
> Sure, let me use GCC 6.2 to reduce SPL image size in upstream rather than compiling-off
> D-cache code.
> 
> But I still don't see ls1088ardb sd boot support in upstream.
> 
> Ashish,
> 
> By when can I expect ls1088ardb sd boot support in upstream?
> 

Sumit,

SD boot is not completed. I don't see RCW in the final image. Pending
Ashish's investigation.

York
Sumit Garg Oct. 5, 2017, 7:55 a.m. UTC | #4 
> -----Original Message-----
> From: York Sun
> Sent: Thursday, October 05, 2017 12:12 AM
> To: Sumit Garg <sumit.garg@nxp.com>; u-boot@lists.denx.de
> Cc: Ruchika Gupta <ruchika.gupta@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>
> Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
> 
> On 10/03/2017 03:51 AM, Sumit Garg wrote:
> >> -----Original Message-----
> >> From: York Sun
> >> Sent: Friday, September 15, 2017 2:08 AM
> >> To: Sumit Garg <sumit.garg@nxp.com>; u-boot@lists.denx.de
> >> Cc: Ruchika Gupta <ruchika.gupta@nxp.com>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>
> >> Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
> >>
> >> On 08/29/2017 12:01 AM, Sumit Garg wrote:
> >>> Using changes in this patch we were able to reduce approx 4k size of
> >>> u-boot-spl.bin image. Following is breif description of changes to
> >>> reduce SPL size:
> >>> 1. Compile-off mp.c and libfdt.c in case of SPL build.
> >>> 2. Keep MMU and DCACHE specific variable and functions under
> >>>     CONFIG_SYS_DCACHE_OFF macro.
> >>> 3. Compile-off IFC specific funtion call "init_early_memctl_regs"
> >>>     in case of SPL build.
> >>>
> >>> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
> >>> ---
> >>>
> >>> Dependent on ls1088 base SD boot target. Also dependent on ls1088
> >>> QPSI secure boot target.
> >>
> >> I don't agree D-cache should be off for SPL boot. Please find other
> >> way to reduce SPL image size.
> >>
> >> York
> >
> > Sure, let me use GCC 6.2 to reduce SPL image size in upstream rather
> > than compiling-off D-cache code.
> >
> > But I still don't see ls1088ardb sd boot support in upstream.
> >
> > Ashish,
> >
> > By when can I expect ls1088ardb sd boot support in upstream?
> >
> 
> Sumit,
> 
> SD boot is not completed. I don't see RCW in the final image. Pending Ashish's
> investigation.
> 
> York
 
I will wait for SD boot patches to be accepted in upstream. As reducing SPL size
for ls1088ardb in upstream does only makes sense once we have base platform
support merged in upstream.

Sumit
York Sun Nov. 29, 2017, 6:36 p.m. UTC | #5 
On 10/05/2017 12:55 AM, Sumit Garg wrote:
>  
> I will wait for SD boot patches to be accepted in upstream. As reducing SPL size
> for ls1088ardb in upstream does only makes sense once we have base platform
> support merged in upstream.
> 

Please rework this patch set.

York
Sumit Garg Nov. 30, 2017, 3:55 p.m. UTC | #6 
> -----Original Message-----
> From: York Sun
> Sent: Thursday, November 30, 2017 12:07 AM
> To: Sumit Garg <sumit.garg@nxp.com>; u-boot@lists.denx.de
> Cc: Ruchika Gupta <ruchika.gupta@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>
> Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
> 
> On 10/05/2017 12:55 AM, Sumit Garg wrote:
> >
> > I will wait for SD boot patches to be accepted in upstream. As
> > reducing SPL size for ls1088ardb in upstream does only makes sense
> > once we have base platform support merged in upstream.
> >
> 
> Please rework this patch set.
> 
> York

Sure, I will pick it up. Actually I am currently occupied in some other work.

Sumit
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 115c3fc..0cb6d4e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,8 +7,10 @@ 
 obj-y += cpu.o
 obj-y += lowlevel.o
 obj-y += soc.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+endif
 obj-$(CONFIG_SPL) += spl.o
 obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3c9a5ed..3ce51af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -32,7 +32,9 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_DCACHE_OFF
 struct mm_region *mem_map = early_map;
+#endif
 
 void cpu_name(char *name)
 {
@@ -824,6 +826,7 @@  void efi_add_known_memory(void)
 }
 #endif
 
+#ifndef CONFIG_SYS_DCACHE_OFF
 /*
  * Before DDR size is known, early MMU table have DDR mapped as device memory
  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
@@ -888,14 +891,17 @@  void update_early_mmu_table(void)
 		}
 	}
 }
+#endif
 
 __weak int dram_init(void)
 {
 	fsl_initdram();
+#ifndef CONFIG_SYS_DCACHE_OFF
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
 #endif
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2075c96..7c26953 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -329,7 +329,9 @@  void bypass_smmu(void)
 void fsl_lsch3_early_init_f(void)
 {
 	erratum_rcw_src();
+#ifndef CONFIG_SPL_BUILD
 	init_early_memctl_regs();	/* tighten IFC timing */
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 	erratum_a009203();
 #endif