| Message ID | 1476347589-5578-6-git-send-email-clsee@altera.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Marek Vasut |
| Headers | show |
On 10/13/2016 10:33 AM, Chin Liang See wrote: > Disable the FPGA Manager for Stratix 10 SoC as we are not > using this for SOCVP If it's not used on SoCVP, then shouldn't this be disabled only for SoCVP instead of S10 ? > Signed-off-by: Chin Liang See <clsee@altera.com> > Cc: Marek Vasut <marex@denx.de> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Ley Foon Tan <lftan@altera.com> > Cc: Tien Fong Chee <tfchee@altera.com> > --- > arch/arm/mach-socfpga/Makefile | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > index 809cd47..a8ea277 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -8,12 +8,13 @@ > # > > obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ > - fpga_manager.o board.o > + board.o > > obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o > > # QTS-generated config file wrappers > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ > + fpga_manager.o > obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ > wrap_sdram_config.o > CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) >
On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > Disable the FPGA Manager for Stratix 10 SoC as we are not > > using this for SOCVP > If it's not used on SoCVP, then shouldn't this be disabled only for > SoCVP instead of S10 ? > We will be enhancing this code to support the hardware / emulation in later phase. In another word, will switch the support from SOCVP to hardware once its available. Thanks Chin Liang > > > > Signed-off-by: Chin Liang See <clsee@altera.com> > > Cc: Marek Vasut <marex@denx.de> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > Cc: Ley Foon Tan <lftan@altera.com> > > Cc: Tien Fong Chee <tfchee@altera.com> > > --- > > arch/arm/mach-socfpga/Makefile | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- > > socfpga/Makefile > > index 809cd47..a8ea277 100644 > > --- a/arch/arm/mach-socfpga/Makefile > > +++ b/arch/arm/mach-socfpga/Makefile > > @@ -8,12 +8,13 @@ > > # > > > > obj-y += misc.o timer.o reset_manager.o system_manager.o > > clock_manager.o \ > > - fpga_manager.o board.o > > + board.o > > > > obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o > > > > # QTS-generated config file wrappers > > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o > > wrap_pll_config.o > > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o > > wrap_pll_config.o \ > > + fpga_manager.o > > obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o > > wrap_pinmux_config.o \ > > wrap_sdram_config.o > > CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) > > > > -- > Best regards, > Marek Vasut > > ________________________________ > > Confidentiality Notice. > This message may contain information that is confidential or > otherwise protected from disclosure. If you are not the intended > recipient, you are hereby notified that any use, disclosure, > dissemination, distribution, or copying of this message, or any > attachments, is strictly prohibited. If you have received this > message in error, please advise the sender by reply e-mail, and > delete the message and any attachments. Thank you.
On 10/17/2016 03:35 PM, See, Chin Liang wrote: > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: >> On 10/13/2016 10:33 AM, Chin Liang See wrote: >>> >>> Disable the FPGA Manager for Stratix 10 SoC as we are not >>> using this for SOCVP >> If it's not used on SoCVP, then shouldn't this be disabled only for >> SoCVP instead of S10 ? >> > > We will be enhancing this code to support the hardware / emulation in > later phase. In another word, will switch the support from SOCVP to > hardware once its available. > This is confusing, what would happen if someone tries to use old u-boot on real hardware ?
On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > On 10/17/2016 03:35 PM, See, Chin Liang wrote: > > > > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > > > > > > > > > Disable the FPGA Manager for Stratix 10 SoC as we are not > > > > using this for SOCVP > > > If it's not used on SoCVP, then shouldn't this be disabled only > > > for > > > SoCVP instead of S10 ? > > > > > We will be enhancing this code to support the hardware / emulation > > in > > later phase. In another word, will switch the support from SOCVP to > > hardware once its available. > > > This is confusing, what would happen if someone tries to use old u- > boot > on real hardware ? It won't work until added drivers for Clocks, Reset and DDR. Current state would be good for SOCVP only where not all hardware is simulated. Thanks Chin Liang > > -- > Best regards, > Marek Vasut >
On 10/17/2016 05:14 PM, Chin Liang See wrote: > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: >> On 10/17/2016 03:35 PM, See, Chin Liang wrote: >>> >>> On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: >>>> >>>> On 10/13/2016 10:33 AM, Chin Liang See wrote: >>>>> >>>>> >>>>> Disable the FPGA Manager for Stratix 10 SoC as we are not >>>>> using this for SOCVP >>>> If it's not used on SoCVP, then shouldn't this be disabled only >>>> for >>>> SoCVP instead of S10 ? >>>> >>> We will be enhancing this code to support the hardware / emulation >>> in >>> later phase. In another word, will switch the support from SOCVP to >>> hardware once its available. >>> >> This is confusing, what would happen if someone tries to use old u- >> boot >> on real hardware ? > > It won't work until added drivers for Clocks, Reset and DDR. Current > state would be good for SOCVP only where not all hardware is simulated. In that case, mark it as SoCVP to prevent confusion please.
On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote: > On 10/17/2016 05:14 PM, Chin Liang See wrote: > > > > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > > > > > > On 10/17/2016 03:35 PM, See, Chin Liang wrote: > > > > > > > > > > > > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > > > > > > > > > > > > > > > > > > > > > Disable the FPGA Manager for Stratix 10 SoC as we are not > > > > > > using this for SOCVP > > > > > If it's not used on SoCVP, then shouldn't this be disabled > > > > > only > > > > > for > > > > > SoCVP instead of S10 ? > > > > > > > > > We will be enhancing this code to support the hardware / > > > > emulation > > > > in > > > > later phase. In another word, will switch the support from > > > > SOCVP to > > > > hardware once its available. > > > > > > > This is confusing, what would happen if someone tries to use old > > > u- > > > boot > > > on real hardware ? > > It won't work until added drivers for Clocks, Reset and DDR. > > Current > > state would be good for SOCVP only where not all hardware is > > simulated. > In that case, mark it as SoCVP to prevent confusion please. > In this case, I can update the config to indicate this is S10 SOCVP. Thanks Chin Liang > > -- > Best regards, > Marek Vasut > > ________________________________ > > Confidentiality Notice. > This message may contain information that is confidential or > otherwise protected from disclosure. If you are not the intended > recipient, you are hereby notified that any use, disclosure, > dissemination, distribution, or copying of this message, or any > attachments, is strictly prohibited. If you have received this > message in error, please advise the sender by reply e-mail, and > delete the message and any attachments. Thank you.
On 10/17/2016 05:30 PM, Chin Liang See wrote: > On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote: >> On 10/17/2016 05:14 PM, Chin Liang See wrote: >>> >>> On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: >>>> >>>> On 10/17/2016 03:35 PM, See, Chin Liang wrote: >>>>> >>>>> >>>>> On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: >>>>>> >>>>>> >>>>>> On 10/13/2016 10:33 AM, Chin Liang See wrote: >>>>>>> >>>>>>> >>>>>>> >>>>>>> Disable the FPGA Manager for Stratix 10 SoC as we are not >>>>>>> using this for SOCVP >>>>>> If it's not used on SoCVP, then shouldn't this be disabled >>>>>> only >>>>>> for >>>>>> SoCVP instead of S10 ? >>>>>> >>>>> We will be enhancing this code to support the hardware / >>>>> emulation >>>>> in >>>>> later phase. In another word, will switch the support from >>>>> SOCVP to >>>>> hardware once its available. >>>>> >>>> This is confusing, what would happen if someone tries to use old >>>> u- >>>> boot >>>> on real hardware ? >>> It won't work until added drivers for Clocks, Reset and DDR. >>> Current >>> state would be good for SOCVP only where not all hardware is >>> simulated. >> In that case, mark it as SoCVP to prevent confusion please. >> > > In this case, I can update the config to indicate this is S10 SOCVP. > Yes please.
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47..a8ea277 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,12 +8,13 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o board.o + board.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ + fpga_manager.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
Disable the FPGA Manager for Stratix 10 SoC as we are not using this for SOCVP Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Tien Fong Chee <tfchee@altera.com> --- arch/arm/mach-socfpga/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)