| Message ID | 1473653331-6545-2-git-send-email-Zhiqiang.Hou@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
> -----Original Message----- > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] > Sent: Monday, September 12, 2016 9:39 AM > To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson > <calvin.johnson@nxp.com> > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > This patch map the sys_info->freq_systembus to Platform PLL, and > implement the IPs' clock function individually. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 +++++++++++++++++-- > --- > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > include/configs/ls2080a_common.h | 2 +- > 3 files changed, 22 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > index a9b12a4..daad80a 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) > #endif > #endif > > + /* The freq_systembus is used to record frequency of platform PLL */ > sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; > - /* Platform clock is half of platform PLL */ > - sys_info->freq_systembus /= 2; This is required only for ls2080A and ls2088A otherwise u-boot will be printing dicken speed in boot log. > sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) > ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); > ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; > > - sys_info->freq_localbus = sys_info->freq_systembus / ccr; > + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; > #endif > } > > @@ -159,7 +158,7 @@ int get_clocks(void) > > /******************************************** > * get_bus_freq > - * return system bus freq in Hz > + * return platform PLL freq in Hz > *********************************************/ > ulong get_bus_freq(ulong dummy) > { > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) > return gd->mem_clk; > } > > +int get_i2c_freq(ulong dummy) > +{ > + return get_bus_freq(0) / 4; > +} > + > +int get_dspi_freq(ulong dummy) > +{ > + return get_bus_freq(0) / 4; > +} > + > +int get_serial_clock(void) > +{ > + return get_bus_freq(0) / 4; > +} > + get_bus_freq(0) / 4 --> May not be true for LS1088A. So Avoid this for above code. --prabhakar
Hi Prabhakar, Thanks for your feedback. > -----Original Message----- > From: Prabhakar Kushwaha > Sent: 2016年9月13日 15:22 > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > initialization > > > > -----Original Message----- > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] > > Sent: Monday, September 12, 2016 9:39 AM > > To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson > > <calvin.johnson@nxp.com> > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > initialization > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > This patch map the sys_info->freq_systembus to Platform PLL, and > > implement the IPs' clock function individually. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 > > +++++++++++++++++-- > > --- > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > > include/configs/ls2080a_common.h | 2 +- > > 3 files changed, 22 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > index a9b12a4..daad80a 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) > > #endif #endif > > > > + /* The freq_systembus is used to record frequency of platform PLL */ > > sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; > > - /* Platform clock is half of platform PLL */ > > - sys_info->freq_systembus /= 2; > > This is required only for ls2080A and ls2088A otherwise u-boot will be printing > dicken speed in boot log. Why it is required by ls2080A and ls2088A? and I don't know what's 'dicken speed'? > > > sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) > > ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); > > ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; > > > > - sys_info->freq_localbus = sys_info->freq_systembus / ccr; > > + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; > > #endif > > } > > > > @@ -159,7 +158,7 @@ int get_clocks(void) > > > > /******************************************** > > * get_bus_freq > > - * return system bus freq in Hz > > + * return platform PLL freq in Hz > > *********************************************/ > > ulong get_bus_freq(ulong dummy) > > { > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) > > return gd->mem_clk; > > } > > > > +int get_i2c_freq(ulong dummy) > > +{ > > + return get_bus_freq(0) / 4; > > +} > > + > > +int get_dspi_freq(ulong dummy) > > +{ > > + return get_bus_freq(0) / 4; > > +} > > + > > +int get_serial_clock(void) > > +{ > > + return get_bus_freq(0) / 4; > > +} > > + > > get_bus_freq(0) / 4 --> May not be true for LS1088A. So Avoid this for above > code. Will take LS1088A into account. Thanks, Zhiqiang
> -----Original Message----- > From: Z.Q. Hou > Sent: Tuesday, September 13, 2016 2:39 PM > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u- > boot@lists.denx.de; albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; > Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > initialization > > Hi Prabhakar, > > Thanks for your feedback. > > > -----Original Message----- > > From: Prabhakar Kushwaha > > Sent: 2016年9月13日 15:22 > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > initialization > > > > > > > -----Original Message----- > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] > > > Sent: Monday, September 12, 2016 9:39 AM > > > To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson > > > <calvin.johnson@nxp.com> > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > > initialization > > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > This patch map the sys_info->freq_systembus to Platform PLL, and > > > implement the IPs' clock function individually. > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > --- > > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 > > > +++++++++++++++++-- > > > --- > > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > > > include/configs/ls2080a_common.h | 2 +- > > > 3 files changed, 22 insertions(+), 7 deletions(-) > > > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > index a9b12a4..daad80a 100644 > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) > > > #endif #endif > > > > > > + /* The freq_systembus is used to record frequency of platform PLL */ > > > sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; > > > - /* Platform clock is half of platform PLL */ > > > - sys_info->freq_systembus /= 2; > > > > This is required only for ls2080A and ls2088A otherwise u-boot will be printing > > dicken speed in boot log. > > Why it is required by ls2080A and ls2088A? and I don't know what's 'dicken > speed'? > Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080 and LS2088A. Platform clock or CCB = dicken speed/2 > > > > > sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) > > > ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); > > > ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; > > > > > > - sys_info->freq_localbus = sys_info->freq_systembus / ccr; > > > + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; > > > #endif > > > } > > > > > > @@ -159,7 +158,7 @@ int get_clocks(void) > > > > > > /******************************************** > > > * get_bus_freq > > > - * return system bus freq in Hz > > > + * return platform PLL freq in Hz > > > *********************************************/ > > > ulong get_bus_freq(ulong dummy) > > > { > > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) > > > return gd->mem_clk; > > > } > > > > > > +int get_i2c_freq(ulong dummy) > > > +{ > > > + return get_bus_freq(0) / 4; > > > +} > > > + > > > +int get_dspi_freq(ulong dummy) > > > +{ > > > + return get_bus_freq(0) / 4; > > > +} > > > + > > > +int get_serial_clock(void) > > > +{ > > > + return get_bus_freq(0) / 4; > > > +} > > > + > > > > get_bus_freq(0) / 4 --> May not be true for LS1088A. So Avoid this for above > > code. > > Will take LS1088A into account. > Thanks --prabhakar
Hi Prabhakar, Thanks for your feedback! > -----Original Message----- > From: Prabhakar Kushwaha > Sent: 2016年9月13日 18:04 > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > initialization > > > > -----Original Message----- > > From: Z.Q. Hou > > Sent: Tuesday, September 13, 2016 2:39 PM > > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u- > > boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson > > <calvin.johnson@nxp.com> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > initialization > > > > Hi Prabhakar, > > > > Thanks for your feedback. > > > > > -----Original Message----- > > > From: Prabhakar Kushwaha > > > Sent: 2016年9月13日 15:22 > > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > > > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock > > > system initialization > > > > > > > > > > -----Original Message----- > > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] > > > > Sent: Monday, September 12, 2016 9:39 AM > > > > To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar > > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson > > > > <calvin.johnson@nxp.com> > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > > > initialization > > > > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > > > This patch map the sys_info->freq_systembus to Platform PLL, and > > > > implement the IPs' clock function individually. > > > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > --- > > > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 > > > > +++++++++++++++++-- > > > > --- > > > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > > > > include/configs/ls2080a_common.h | 2 +- > > > > 3 files changed, 22 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > index a9b12a4..daad80a 100644 > > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) > > > > #endif #endif > > > > > > > > + /* The freq_systembus is used to record frequency of platform > > > > +PLL */ > > > > sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> > > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & > > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; > > > > - /* Platform clock is half of platform PLL */ > > > > - sys_info->freq_systembus /= 2; > > > > > > This is required only for ls2080A and ls2088A otherwise u-boot will > > > be printing dicken speed in boot log. > > > > Why it is required by ls2080A and ls2088A? and I don't know what's > > 'dicken speed'? > > > > Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080 > and LS2088A. > Platform clock or CCB = dicken speed/2 Why it is required by ls2080A and ls2088A but without #ifdef LS2080||LS2088? Is there any document upon the concept 'dicken speed'? As you said the dicken speed == platform PLL frequency on LS2080A and LS2088A, what about other SoCs? if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3? > > > > > > > > sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> > > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) > > > > ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); > > > > ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) > + > > > > 1; > > > > > > > > - sys_info->freq_localbus = sys_info->freq_systembus / ccr; > > > > + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; > > > > #endif > > > > } > > > > > > > > @@ -159,7 +158,7 @@ int get_clocks(void) > > > > > > > > /******************************************** > > > > * get_bus_freq > > > > - * return system bus freq in Hz > > > > + * return platform PLL freq in Hz > > > > *********************************************/ > > > > ulong get_bus_freq(ulong dummy) > > > > { > > > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) > > > > return gd->mem_clk; > > > > } > > > > > > > > +int get_i2c_freq(ulong dummy) > > > > +{ > > > > + return get_bus_freq(0) / 4; > > > > +} > > > > + > > > > +int get_dspi_freq(ulong dummy) > > > > +{ > > > > + return get_bus_freq(0) / 4; > > > > +} > > > > + > > > > +int get_serial_clock(void) > > > > +{ > > > > + return get_bus_freq(0) / 4; > > > > +} > > > > + > > > > > > get_bus_freq(0) / 4 --> May not be true for LS1088A. So Avoid this > > > for above code. > > > > Will take LS1088A into account. > > > Thanks > Thanks, Zhiqiang
> -----Original Message----- > From: Z.Q. Hou > Sent: Wednesday, September 14, 2016 8:16 AM > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u- > boot@lists.denx.de; albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; > Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > initialization > > Hi Prabhakar, > > Thanks for your feedback! > > > -----Original Message----- > > From: Prabhakar Kushwaha > > Sent: 2016年9月13日 18:04 > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > initialization > > > > > > > -----Original Message----- > > > From: Z.Q. Hou > > > Sent: Tuesday, September 13, 2016 2:39 PM > > > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u- > > > boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson > > > <calvin.johnson@nxp.com> > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > > initialization > > > > > > Hi Prabhakar, > > > > > > Thanks for your feedback. > > > > > > > -----Original Message----- > > > > From: Prabhakar Kushwaha > > > > Sent: 2016年9月13日 15:22 > > > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > > > > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > > > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock > > > > system initialization > > > > > > > > > > > > > -----Original Message----- > > > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] > > > > > Sent: Monday, September 12, 2016 9:39 AM > > > > > To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar > > > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson > > > > > <calvin.johnson@nxp.com> > > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > > > > initialization > > > > > > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > > > > > This patch map the sys_info->freq_systembus to Platform PLL, and > > > > > implement the IPs' clock function individually. > > > > > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > --- > > > > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 > > > > > +++++++++++++++++-- > > > > > --- > > > > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > > > > > include/configs/ls2080a_common.h | 2 +- > > > > > 3 files changed, 22 insertions(+), 7 deletions(-) > > > > > > > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > index a9b12a4..daad80a 100644 > > > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) > > > > > #endif #endif > > > > > > > > > > + /* The freq_systembus is used to record frequency of platform > > > > > +PLL */ > > > > > sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> > > > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & > > > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; > > > > > - /* Platform clock is half of platform PLL */ > > > > > - sys_info->freq_systembus /= 2; > > > > > > > > This is required only for ls2080A and ls2088A otherwise u-boot will > > > > be printing dicken speed in boot log. > > > > > > Why it is required by ls2080A and ls2088A? and I don't know what's > > > 'dicken speed'? > > > > > > > Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080 > > and LS2088A. > > Platform clock or CCB = dicken speed/2 > > Why it is required by ls2080A and ls2088A but without #ifdef LS2080||LS2088? > Is there any document upon the concept 'dicken speed'? As you said the dicken > speed == platform PLL frequency on LS2080A and LS2088A, what about other > SoCs? > if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3? > Platform clock == dicken speed/2. It is only for LS2080A and LS2088A. For ls1088a and other SoCs platform clock = SYSCLK * RCW[SYS_PLL_RAT] > > > > > > > > > > > sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> > > > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > > > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > > > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) > > > > > ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); > > > > > ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) > > + > > > > > 1; > > > > > > > > > > - sys_info->freq_localbus = sys_info->freq_systembus / ccr; > > > > > + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; > > > > > #endif > > > > > } > > > > > > > > > > @@ -159,7 +158,7 @@ int get_clocks(void) > > > > > > > > > > /******************************************** > > > > > * get_bus_freq > > > > > - * return system bus freq in Hz > > > > > + * return platform PLL freq in Hz > > > > > *********************************************/ > > > > > ulong get_bus_freq(ulong dummy) > > > > > { > > > > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) > > > > > return gd->mem_clk; > > > > > } > > > > > > > > > > +int get_i2c_freq(ulong dummy) > > > > > +{ > > > > > + return get_bus_freq(0) / 4; > > > > > +} > > > > > + > > > > > +int get_dspi_freq(ulong dummy) > > > > > +{ > > > > > + return get_bus_freq(0) / 4; > > > > > +} > > > > > + > > > > > +int get_serial_clock(void) > > > > > +{ > > > > > + return get_bus_freq(0) / 4; > > > > > +} > > > > > + > > > > > > > > get_bus_freq(0) / 4 --> May not be true for LS1088A. So Avoid this > > > > for above code. > > > > > > Will take LS1088A into account. > > > > > Thanks > > > > Thanks, > Zhiqiang
Hi Prabhakar, > -----Original Message----- > From: Prabhakar Kushwaha > Sent: 2016年9月14日 16:18 > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Mingkai Hu > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > initialization > > > > -----Original Message----- > > From: Z.Q. Hou > > Sent: Wednesday, September 14, 2016 8:16 AM > > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u- > > boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson > > <calvin.johnson@nxp.com> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system > > initialization > > > > Hi Prabhakar, > > > > Thanks for your feedback! > > > > > -----Original Message----- > > > From: Prabhakar Kushwaha > > > Sent: 2016年9月13日 18:04 > > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > > > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu > > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock > > > system initialization > > > > > > > > > > -----Original Message----- > > > > From: Z.Q. Hou > > > > Sent: Tuesday, September 13, 2016 2:39 PM > > > > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u- > > > > boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin > > > > Johnson <calvin.johnson@nxp.com> > > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock > > > > system initialization > > > > > > > > Hi Prabhakar, > > > > > > > > Thanks for your feedback. > > > > > > > > > -----Original Message----- > > > > > From: Prabhakar Kushwaha > > > > > Sent: 2016年9月13日 15:22 > > > > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; > > > > > albert.u.boot@aribaud.net; york sun <york.sun@nxp.com>; Vincent > > > > > Hu <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com> > > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock > > > > > system initialization > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] > > > > > > Sent: Monday, September 12, 2016 9:39 AM > > > > > > To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun > > > > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar > > > > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson > > > > > > <calvin.johnson@nxp.com> > > > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com> > > > > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock > > > > > > system initialization > > > > > > > > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > > > > > > > This patch map the sys_info->freq_systembus to Platform PLL, > > > > > > and implement the IPs' clock function individually. > > > > > > > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > > --- > > > > > > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 > > > > > > +++++++++++++++++-- > > > > > > --- > > > > > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + > > > > > > include/configs/ls2080a_common.h | 2 +- > > > > > > 3 files changed, 22 insertions(+), 7 deletions(-) > > > > > > > > > > > > diff --git > > > > > > a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > > index a9b12a4..daad80a 100644 > > > > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c > > > > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info > > > > > > *sys_info) #endif #endif > > > > > > > > > > > > + /* The freq_systembus is used to record frequency of > > > > > > +platform PLL */ > > > > > > sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> > > > > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & > > > > > > FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; > > > > > > - /* Platform clock is half of platform PLL */ > > > > > > - sys_info->freq_systembus /= 2; > > > > > > > > > > This is required only for ls2080A and ls2088A otherwise u-boot > > > > > will be printing dicken speed in boot log. > > > > > > > > Why it is required by ls2080A and ls2088A? and I don't know what's > > > > 'dicken speed'? > > > > > > > > > > Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for > > > LS2080 and LS2088A. > > > Platform clock or CCB = dicken speed/2 > > > > Why it is required by ls2080A and ls2088A but without #ifdef > LS2080||LS2088? > > Is there any document upon the concept 'dicken speed'? As you said the > > dicken speed == platform PLL frequency on LS2080A and LS2088A, what > > about other SoCs? > > if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3? > > > > Platform clock == dicken speed/2. It is only for LS2080A and LS2088A. > For ls1088a and other SoCs platform clock = SYSCLK * RCW[SYS_PLL_RAT] > Refer to LS1012A RM revC, the ls1012a platform clock = SYSCLK * RCW[SYS_PLL_RAT] / 2. For this patch, what do you think about matching sys_info->freq_systembus with platform PLL frequency? Do you have any suggestion on either the platform PLL or platform clock should be printed as bus clock in u-boot? > > > > > > > > > > > > > > sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> > > > > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & > > > > > > FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; > > > > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) > > > > > > ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); > > > > > > ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> > > > > > > IFC_CCR_CLK_DIV_SHIFT) > > > + > > > > > > 1; > > > > > > > > > > > > - sys_info->freq_localbus = sys_info->freq_systembus / ccr; > > > > > > + sys_info->freq_localbus = sys_info->freq_systembus / 2 / > > > > > > +ccr; > > > > > > #endif > > > > > > } > > > > > > > > > > > > @@ -159,7 +158,7 @@ int get_clocks(void) > > > > > > > > > > > > /******************************************** > > > > > > * get_bus_freq > > > > > > - * return system bus freq in Hz > > > > > > + * return platform PLL freq in Hz > > > > > > *********************************************/ > > > > > > ulong get_bus_freq(ulong dummy) { @@ -190,13 +189,28 @@ > > > > > > ulong get_ddr_freq(ulong ctrl_num) > > > > > > return gd->mem_clk; > > > > > > } > > > > > > > > > > > > +int get_i2c_freq(ulong dummy) { > > > > > > + return get_bus_freq(0) / 4; } > > > > > > + > > > > > > +int get_dspi_freq(ulong dummy) { > > > > > > + return get_bus_freq(0) / 4; } > > > > > > + > > > > > > +int get_serial_clock(void) > > > > > > +{ > > > > > > + return get_bus_freq(0) / 4; > > > > > > +} > > > > > > + > > > > > > > > > > get_bus_freq(0) / 4 --> May not be true for LS1088A. So Avoid > > > > > this for above code. > > > > > > > > Will take LS1088A into account. > > > > > > > Thanks > > > Thanks, Zhiqiang
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a9b12a4..daad80a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) #endif #endif + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; - /* Platform clock is half of platform PLL */ - sys_info->freq_systembus /= 2; sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; #endif } @@ -159,7 +158,7 @@ int get_clocks(void) /******************************************** * get_bus_freq - * return system bus freq in Hz + * return platform PLL freq in Hz *********************************************/ ulong get_bus_freq(ulong dummy) { @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) return gd->mem_clk; } +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / 4; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / 4; +} + +int get_serial_clock(void) +{ + return get_bus_freq(0) / 4; +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0) / 2; + return get_i2c_freq(0); case MXC_DSPI_CLK: - return get_bus_freq(0) / 2; + return get_dspi_freq(0); default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 93e26c1..5415165 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -165,6 +165,7 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index ebe1415..8cfb7fb 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -102,7 +102,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }