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[U-Boot,v2,9/9] board: odroid-c2: add Ethernet support

Message ID 1459667897-2824-10-git-send-email-b.galvani@gmail.com
State Changes Requested
Delegated to: Tom Rini
Headers show

Commit Message

Beniamino Galvani April 3, 2016, 7:18 a.m. UTC
Add initialization code for the Ethernet adapter on ODROID-C2 and
enable the driver.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
---
 arch/arm/include/asm/arch-meson/gxbb.h | 54 ++++++++++++++++++++++++++++++++++
 board/hardkernel/odroid-c2/odroid-c2.c | 25 ++++++++++++++++
 configs/odroid-c2_defconfig            |  3 ++
 include/configs/odroid-c2.h            |  1 +
 4 files changed, 83 insertions(+)

Comments

Tom Rini April 3, 2016, 4:09 p.m. UTC | #1
On Sun, Apr 03, 2016 at 09:18:17AM +0200, Beniamino Galvani wrote:

> Add initialization code for the Ethernet adapter on ODROID-C2 and
> enable the driver.
> 
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>

For the contents:

Reviewed-by: Tom Rini <trini@konsulko.com>
Joe Hershberger April 4, 2016, 12:20 a.m. UTC | #2
On Sun, Apr 3, 2016 at 2:18 AM, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Add initialization code for the Ethernet adapter on ODROID-C2 and
> enable the driver.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> ---
>  arch/arm/include/asm/arch-meson/gxbb.h | 54 ++++++++++++++++++++++++++++++++++
>  board/hardkernel/odroid-c2/odroid-c2.c | 25 ++++++++++++++++
>  configs/odroid-c2_defconfig            |  3 ++
>  include/configs/odroid-c2.h            |  1 +
>  4 files changed, 83 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
> index 0eec270..59fae9f 100644
> --- a/arch/arm/include/asm/arch-meson/gxbb.h
> +++ b/arch/arm/include/asm/arch-meson/gxbb.h
> @@ -7,4 +7,58 @@
>  #ifndef __GXBB_H__
>  #define __GXBB_H__
>
> +#define GXBB_PERIPHS_BASE      0xc8834400
> +#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
> +
> +#define GXBB_GPIO_0_EN         GXBB_PERIPHS_ADDR(0x0c)
> +#define GXBB_GPIO_0_OUT                GXBB_PERIPHS_ADDR(0x0d)
> +#define GXBB_GPIO_0_IN         GXBB_PERIPHS_ADDR(0x0e)
> +#define GXBB_GPIO_1_EN         GXBB_PERIPHS_ADDR(0x0f)
> +#define GXBB_GPIO_1_OUT                GXBB_PERIPHS_ADDR(0x10)
> +#define GXBB_GPIO_1_IN         GXBB_PERIPHS_ADDR(0x11)
> +#define GXBB_GPIO_2_EN         GXBB_PERIPHS_ADDR(0x12)
> +#define GXBB_GPIO_2_OUT                GXBB_PERIPHS_ADDR(0x13)
> +#define GXBB_GPIO_2_IN         GXBB_PERIPHS_ADDR(0x14)
> +#define GXBB_GPIO_3_EN         GXBB_PERIPHS_ADDR(0x15)
> +#define GXBB_GPIO_3_OUT                GXBB_PERIPHS_ADDR(0x16)
> +#define GXBB_GPIO_3_IN         GXBB_PERIPHS_ADDR(0x17)
> +#define GXBB_GPIO_4_EN         GXBB_PERIPHS_ADDR(0x18)
> +#define GXBB_GPIO_4_OUT                GXBB_PERIPHS_ADDR(0x19)
> +#define GXBB_GPIO_4_IN         GXBB_PERIPHS_ADDR(0x1a)
> +#define GXBB_GPIO_5_EN         GXBB_PERIPHS_ADDR(0x1b)
> +#define GXBB_GPIO_5_OUT                GXBB_PERIPHS_ADDR(0x1c)
> +#define GXBB_GPIO_5_IN         GXBB_PERIPHS_ADDR(0x1d)
> +#define GXBB_GPIO_6_EN         GXBB_PERIPHS_ADDR(0x08)
> +#define GXBB_GPIO_6_OUT                GXBB_PERIPHS_ADDR(0x09)
> +#define GXBB_GPIO_6_IN         GXBB_PERIPHS_ADDR(0x0a)
> +
> +#define GXBB_PINMUX_0          GXBB_PERIPHS_ADDR(0x2c)
> +#define GXBB_PINMUX_1          GXBB_PERIPHS_ADDR(0x2d)
> +#define GXBB_PINMUX_2          GXBB_PERIPHS_ADDR(0x2e)
> +#define GXBB_PINMUX_3          GXBB_PERIPHS_ADDR(0x2f)
> +#define GXBB_PINMUX_4          GXBB_PERIPHS_ADDR(0x30)
> +#define GXBB_PINMUX_5          GXBB_PERIPHS_ADDR(0x31)
> +#define GXBB_PINMUX_6          GXBB_PERIPHS_ADDR(0x32)
> +#define GXBB_PINMUX_7          GXBB_PERIPHS_ADDR(0x33)
> +#define GXBB_PINMUX_8          GXBB_PERIPHS_ADDR(0x34)
> +#define GXBB_PINMUX_9          GXBB_PERIPHS_ADDR(0x35)
> +#define GXBB_PINMUX_10         GXBB_PERIPHS_ADDR(0x36)
> +#define GXBB_PINMUX_11         GXBB_PERIPHS_ADDR(0x37)
> +#define GXBB_PINMUX_12         GXBB_PERIPHS_ADDR(0x38)
> +
> +#define GXBB_ETH_REG_0         GXBB_PERIPHS_ADDR(0x50)
> +#define GXBB_ETH_REG_1         GXBB_PERIPHS_ADDR(0x51)
> +
> +#define GXBB_HIU_BASE          0xc883c000
> +#define GXBB_HIU_ADDR(off)     (GXBB_HIU_BASE + ((off) << 2))
> +
> +#define GXBB_MEM_PD_REG_0      GXBB_HIU_ADDR(0x40)
> +
> +/* Clock gates */
> +#define GXBB_GCLK_MPEG_0       GXBB_HIU_ADDR(0x50)
> +#define GXBB_GCLK_MPEG_1       GXBB_HIU_ADDR(0x51)
> +#define GXBB_GCLK_MPEG_2       GXBB_HIU_ADDR(0x52)
> +#define GXBB_GCLK_MPEG_OTHER   GXBB_HIU_ADDR(0x53)
> +#define GXBB_GCLK_MPEG_AO      GXBB_HIU_ADDR(0x54)
> +
>  #endif /* __GXBB_H__ */
> diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
> index 6a1485f..2d82d11 100644
> --- a/board/hardkernel/odroid-c2/odroid-c2.c
> +++ b/board/hardkernel/odroid-c2/odroid-c2.c
> @@ -5,3 +5,28 @@
>   */
>
>  #include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/gxbb.h>
> +
> +#ifdef CONFIG_MISC_INIT_R
> +int misc_init_r(void)
> +{
> +       /* Select Ethernet function */
> +       setbits_le32(GXBB_PINMUX_6, 0x3fff);
> +
> +       /* Set RGMII mode */
> +       setbits_le32(GXBB_ETH_REG_0, 0x1621);

It would be good to have constants for all these magic numbers.

> +
> +       /* Enable clocks */
> +       setbits_le32(GXBB_GCLK_MPEG_1, 1 << 3);

Use the BIT() macro for this type of thing. Probably use the BIT()
macro in another named macro for the meaning of the magic bit.

> +       clrbits_le32(GXBB_MEM_PD_REG_0, (1 << 3) | (1 << 2));
> +
> +       /* Reset PHY on GPIOZ_14 */
> +       clrbits_le32(GXBB_GPIO_3_EN, 1 << 14);
> +       clrbits_le32(GXBB_GPIO_3_OUT, 1 << 14);
> +       udelay(100000);
> +       setbits_le32(GXBB_GPIO_3_OUT, 1 << 14);
> +
> +       return 0;
> +}
> +#endif /* CONFIG_MISC_INIT_R */
> diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
> index 069f02d..a771b20 100644
> --- a/configs/odroid-c2_defconfig
> +++ b/configs/odroid-c2_defconfig
> @@ -11,6 +11,9 @@ CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
>  # CONFIG_CMD_SOURCE is not set
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_OF_CONTROL=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
>  CONFIG_DEBUG_UART=y
>  CONFIG_DEBUG_UART_MESON=y
>  CONFIG_DEBUG_UART_BASE=0xc81004c0
> diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
> index 0e9ad1c..12bc086 100644
> --- a/include/configs/odroid-c2.h
> +++ b/include/configs/odroid-c2.h
> @@ -19,6 +19,7 @@
>  #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
>  #define CONFIG_SYS_CBSIZE              1024
>  #define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_MISC_INIT_R
>
>  #define CONFIG_SYS_SDRAM_BASE          0
>  #define CONFIG_SYS_TEXT_BASE           0x01000000
> --
> 2.7.3
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Beniamino Galvani April 10, 2016, 3:35 p.m. UTC | #3
On Sun, Apr 03, 2016 at 07:20:10PM -0500, Joe Hershberger wrote:
> > +#ifdef CONFIG_MISC_INIT_R
> > +int misc_init_r(void)
> > +{
> > +       /* Select Ethernet function */
> > +       setbits_le32(GXBB_PINMUX_6, 0x3fff);
> > +
> > +       /* Set RGMII mode */
> > +       setbits_le32(GXBB_ETH_REG_0, 0x1621);
> 
> It would be good to have constants for all these magic numbers.
> 
> > +
> > +       /* Enable clocks */
> > +       setbits_le32(GXBB_GCLK_MPEG_1, 1 << 3);
> 
> Use the BIT() macro for this type of thing. Probably use the BIT()
> macro in another named macro for the meaning of the magic bit.

I updated known values with macros in v3 (but left 0x3fff as is
because its meaning is not documented). Thanks!

Beniamino
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
index 0eec270..59fae9f 100644
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -7,4 +7,58 @@ 
 #ifndef __GXBB_H__
 #define __GXBB_H__
 
+#define GXBB_PERIPHS_BASE	0xc8834400
+#define GXBB_PERIPHS_ADDR(off)	(GXBB_PERIPHS_BASE + ((off) << 2))
+
+#define GXBB_GPIO_0_EN		GXBB_PERIPHS_ADDR(0x0c)
+#define GXBB_GPIO_0_OUT		GXBB_PERIPHS_ADDR(0x0d)
+#define GXBB_GPIO_0_IN		GXBB_PERIPHS_ADDR(0x0e)
+#define GXBB_GPIO_1_EN		GXBB_PERIPHS_ADDR(0x0f)
+#define GXBB_GPIO_1_OUT		GXBB_PERIPHS_ADDR(0x10)
+#define GXBB_GPIO_1_IN		GXBB_PERIPHS_ADDR(0x11)
+#define GXBB_GPIO_2_EN		GXBB_PERIPHS_ADDR(0x12)
+#define GXBB_GPIO_2_OUT		GXBB_PERIPHS_ADDR(0x13)
+#define GXBB_GPIO_2_IN		GXBB_PERIPHS_ADDR(0x14)
+#define GXBB_GPIO_3_EN		GXBB_PERIPHS_ADDR(0x15)
+#define GXBB_GPIO_3_OUT		GXBB_PERIPHS_ADDR(0x16)
+#define GXBB_GPIO_3_IN		GXBB_PERIPHS_ADDR(0x17)
+#define GXBB_GPIO_4_EN		GXBB_PERIPHS_ADDR(0x18)
+#define GXBB_GPIO_4_OUT		GXBB_PERIPHS_ADDR(0x19)
+#define GXBB_GPIO_4_IN		GXBB_PERIPHS_ADDR(0x1a)
+#define GXBB_GPIO_5_EN		GXBB_PERIPHS_ADDR(0x1b)
+#define GXBB_GPIO_5_OUT		GXBB_PERIPHS_ADDR(0x1c)
+#define GXBB_GPIO_5_IN		GXBB_PERIPHS_ADDR(0x1d)
+#define GXBB_GPIO_6_EN		GXBB_PERIPHS_ADDR(0x08)
+#define GXBB_GPIO_6_OUT		GXBB_PERIPHS_ADDR(0x09)
+#define GXBB_GPIO_6_IN		GXBB_PERIPHS_ADDR(0x0a)
+
+#define GXBB_PINMUX_0		GXBB_PERIPHS_ADDR(0x2c)
+#define GXBB_PINMUX_1		GXBB_PERIPHS_ADDR(0x2d)
+#define GXBB_PINMUX_2		GXBB_PERIPHS_ADDR(0x2e)
+#define GXBB_PINMUX_3		GXBB_PERIPHS_ADDR(0x2f)
+#define GXBB_PINMUX_4		GXBB_PERIPHS_ADDR(0x30)
+#define GXBB_PINMUX_5		GXBB_PERIPHS_ADDR(0x31)
+#define GXBB_PINMUX_6		GXBB_PERIPHS_ADDR(0x32)
+#define GXBB_PINMUX_7		GXBB_PERIPHS_ADDR(0x33)
+#define GXBB_PINMUX_8		GXBB_PERIPHS_ADDR(0x34)
+#define GXBB_PINMUX_9		GXBB_PERIPHS_ADDR(0x35)
+#define GXBB_PINMUX_10		GXBB_PERIPHS_ADDR(0x36)
+#define GXBB_PINMUX_11		GXBB_PERIPHS_ADDR(0x37)
+#define GXBB_PINMUX_12		GXBB_PERIPHS_ADDR(0x38)
+
+#define GXBB_ETH_REG_0		GXBB_PERIPHS_ADDR(0x50)
+#define GXBB_ETH_REG_1		GXBB_PERIPHS_ADDR(0x51)
+
+#define GXBB_HIU_BASE		0xc883c000
+#define GXBB_HIU_ADDR(off)	(GXBB_HIU_BASE + ((off) << 2))
+
+#define GXBB_MEM_PD_REG_0	GXBB_HIU_ADDR(0x40)
+
+/* Clock gates */
+#define GXBB_GCLK_MPEG_0	GXBB_HIU_ADDR(0x50)
+#define GXBB_GCLK_MPEG_1	GXBB_HIU_ADDR(0x51)
+#define GXBB_GCLK_MPEG_2	GXBB_HIU_ADDR(0x52)
+#define GXBB_GCLK_MPEG_OTHER	GXBB_HIU_ADDR(0x53)
+#define GXBB_GCLK_MPEG_AO	GXBB_HIU_ADDR(0x54)
+
 #endif /* __GXBB_H__ */
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
index 6a1485f..2d82d11 100644
--- a/board/hardkernel/odroid-c2/odroid-c2.c
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -5,3 +5,28 @@ 
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	/* Select Ethernet function */
+	setbits_le32(GXBB_PINMUX_6, 0x3fff);
+
+	/* Set RGMII mode */
+	setbits_le32(GXBB_ETH_REG_0, 0x1621);
+
+	/* Enable clocks */
+	setbits_le32(GXBB_GCLK_MPEG_1, 1 << 3);
+	clrbits_le32(GXBB_MEM_PD_REG_0, (1 << 3) | (1 << 2));
+
+	/* Reset PHY on GPIOZ_14 */
+	clrbits_le32(GXBB_GPIO_3_EN, 1 << 14);
+	clrbits_le32(GXBB_GPIO_3_OUT, 1 << 14);
+	udelay(100000);
+	setbits_le32(GXBB_GPIO_3_OUT, 1 << 14);
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 069f02d..a771b20 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -11,6 +11,9 @@  CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_MESON=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index 0e9ad1c..12bc086 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -19,6 +19,7 @@ 
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MISC_INIT_R
 
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_SYS_TEXT_BASE		0x01000000