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[U-Boot,v4,01/14] armv8: ls2080: Add SFP Configs for LS2080/LS2085

Message ID 1454995422-31731-2-git-send-email-saksham.jain@nxp.com
State Changes Requested
Delegated to: York Sun
Headers show

Commit Message

Saksham Jain Feb. 9, 2016, 5:23 a.m. UTC 
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
---
Changes for v2:
	- No changes
Changes for v3:
	- No changes
Changes for v4:
	- Cleaned up commit message

 arch/arm/include/asm/arch-fsl-layerscape/config.h      | 4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++
 include/fsl_sfp.h                                      | 3 ++-
 3 files changed, 9 insertions(+), 1 deletion(-)

Comments

York Sun March 18, 2016, 3:36 p.m. UTC | #1 
On 02/08/2016 09:26 PM, Saksham Jain wrote:
> In LS2080/LS2085, SFP is LE and Ver is 3.4

Please spell out little endian and version. Use proper period sign at the end of
sentence.

> The base address is 0x01e80200

Same here.

York
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ff3b1be..997ff00a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -67,6 +67,10 @@ 
 /* SMMU Defintions */
 #define SMMU_BASE			0x05000000 /* GR0 Base */
 
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE			0x04000000
 #define CCI_MN_RNF_NODEID_LIST		0x180
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..f1b021f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,9 @@ 
 #define AHCI_BASE_ADDR1				(CONFIG_SYS_IMMR + 0x02200000)
 #define AHCI_BASE_ADDR2				(CONFIG_SYS_IMMR + 0x02210000)
 
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
+
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 353a123..2976a2c 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -32,7 +32,8 @@ 
 /* Number of SRKH registers */
 #define NUM_SRKH_REGS	8
 
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+#if	defined(CONFIG_SYS_FSL_SFP_VER_3_2) ||	\
+	defined(CONFIG_SYS_FSL_SFP_VER_3_4)
 struct ccsr_sfp_regs {
 	u32 ospr;		/* 0x200 */
 	u32 ospr1;		/* 0x204 */