| Message ID | 1452096695-9474-2-git-send-email-vishnupatekar0510@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Hans de Goede |
| Headers | show |
Hi, On 06-01-16 17:11, Vishnu Patekar wrote: > Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, > Allwinner Homlet 1.2 has DDR3. > > This adds groundwork to support for new DRAM type for A83T. > DRAM_TYPE=3 for DDR3 and 7 for LPDDR3 will passed to SYS_EXTRA_OPTIONS > from respective board defconfig. NACK SYS_EXTRA_OPTIONS is obsolete, please add a DRAM_CONFIG_FOO Kconfig options for this, please also adjust patch 3/3 for this. Regards, Hans > > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c | 11 ++++++++++- > arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 4 +++- > 2 files changed, 13 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c > index d757e40..cac7f43 100644 > --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c > +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c > @@ -25,6 +25,7 @@ struct dram_para { > u8 rank; > u8 rows; > u8 bus_width; > + u8 dram_type; > u16 page_size; > }; > > @@ -34,7 +35,7 @@ static void mctl_set_cr(struct dram_para *para) > (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; > > writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | > - MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | > + MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | > (para->seq ? MCTL_CR_SEQUENCE : 0) | > ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | > MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | > @@ -86,6 +87,7 @@ static void auto_set_timing_para(struct dram_para *para) > { > struct sunxi_mctl_ctl_reg * const mctl_ctl = > (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; > + > u32 reg_val; > > u8 tccd = 2; > @@ -398,6 +400,13 @@ unsigned long sunxi_dram_init(void) > .page_size = 2048, > }; > > +#if defined(CONFIG_MACH_SUN8I_A83T) > +#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7) > + para.dram_type = CONFIG_DRAM_TYPE; > +#else > +#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) > +#endif > +#endif > setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); > > writel(0, (SUNXI_PRCM_BASE + 0x1e8)); > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h > index 2891b71..05b6a89 100644 > --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h > @@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg { > #define MCTL_CR_BUSW8 (0 << 12) > #define MCTL_CR_BUSW16 (1 << 12) > #define MCTL_CR_SEQUENCE (1 << 15) > -#define MCTL_CR_DDR3 (3 << 16) > +#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) > #define MCTL_CR_CHANNEL_MASK (1 << 19) > #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) > #define MCTL_CR_UNKNOWN (0x4 << 20) > @@ -198,4 +198,6 @@ struct sunxi_mctl_ctl_reg { > #define MCTL_MR2 0x18 /* CWL=8 */ > #define MCTL_MR3 0x0 > > +#define DRAM_TYPE_DDR3 3 > +#define DRAM_TYPE_LPDDR3 7 > #endif /* _SUNXI_DRAM_SUN8I_A83T_H */ >
Hello Hans, On Thu, Jan 7, 2016 at 10:01 PM, Hans de Goede <hdegoede@redhat.com> wrote: > Hi, > > On 06-01-16 17:11, Vishnu Patekar wrote: >> >> Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, >> Allwinner Homlet 1.2 has DDR3. >> >> This adds groundwork to support for new DRAM type for A83T. >> DRAM_TYPE=3 for DDR3 and 7 for LPDDR3 will passed to SYS_EXTRA_OPTIONS >> from respective board defconfig. > > > NACK SYS_EXTRA_OPTIONS is obsolete, please add a DRAM_CONFIG_FOO Kconfig > options for this, please also adjust patch 3/3 for this. Okie, will introduce DRAM_TYPE as int in sunxi/boards/Kconfig for A83T. I think, int value is sufficient. 3 for DDR3 and 7 for LPDDR3. Regards, Vishnu > > Regards, > > Hans > > >> >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> >> --- >> arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c | 11 ++++++++++- >> arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 4 +++- >> 2 files changed, 13 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c >> b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c >> index d757e40..cac7f43 100644 >> --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c >> +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c >> @@ -25,6 +25,7 @@ struct dram_para { >> u8 rank; >> u8 rows; >> u8 bus_width; >> + u8 dram_type; >> u16 page_size; >> }; >> >> @@ -34,7 +35,7 @@ static void mctl_set_cr(struct dram_para *para) >> (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; >> >> writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | >> - MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | >> + MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | >> (para->seq ? MCTL_CR_SEQUENCE : 0) | >> ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) >> | >> MCTL_CR_PAGE_SIZE(para->page_size) | >> MCTL_CR_ROW(para->rows) | >> @@ -86,6 +87,7 @@ static void auto_set_timing_para(struct dram_para *para) >> { >> struct sunxi_mctl_ctl_reg * const mctl_ctl = >> (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; >> + >> u32 reg_val; >> >> u8 tccd = 2; >> @@ -398,6 +400,13 @@ unsigned long sunxi_dram_init(void) >> .page_size = 2048, >> }; >> >> +#if defined(CONFIG_MACH_SUN8I_A83T) >> +#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7) >> + para.dram_type = CONFIG_DRAM_TYPE; >> +#else >> +#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) >> +#endif >> +#endif >> setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); >> >> writel(0, (SUNXI_PRCM_BASE + 0x1e8)); >> diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h >> b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h >> index 2891b71..05b6a89 100644 >> --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h >> +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h >> @@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg { >> #define MCTL_CR_BUSW8 (0 << 12) >> #define MCTL_CR_BUSW16 (1 << 12) >> #define MCTL_CR_SEQUENCE (1 << 15) >> -#define MCTL_CR_DDR3 (3 << 16) >> +#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) >> #define MCTL_CR_CHANNEL_MASK (1 << 19) >> #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) >> #define MCTL_CR_UNKNOWN (0x4 << 20) >> @@ -198,4 +198,6 @@ struct sunxi_mctl_ctl_reg { >> #define MCTL_MR2 0x18 /* CWL=8 */ >> #define MCTL_MR3 0x0 >> >> +#define DRAM_TYPE_DDR3 3 >> +#define DRAM_TYPE_LPDDR3 7 >> #endif /* _SUNXI_DRAM_SUN8I_A83T_H */ >> >
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c index d757e40..cac7f43 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c @@ -25,6 +25,7 @@ struct dram_para { u8 rank; u8 rows; u8 bus_width; + u8 dram_type; u16 page_size; }; @@ -34,7 +35,7 @@ static void mctl_set_cr(struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | - MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | + MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | (para->seq ? MCTL_CR_SEQUENCE : 0) | ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | @@ -86,6 +87,7 @@ static void auto_set_timing_para(struct dram_para *para) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u32 reg_val; u8 tccd = 2; @@ -398,6 +400,13 @@ unsigned long sunxi_dram_init(void) .page_size = 2048, }; +#if defined(CONFIG_MACH_SUN8I_A83T) +#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7) + para.dram_type = CONFIG_DRAM_TYPE; +#else +#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) +#endif +#endif setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); writel(0, (SUNXI_PRCM_BASE + 0x1e8)); diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h index 2891b71..05b6a89 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg { #define MCTL_CR_BUSW8 (0 << 12) #define MCTL_CR_BUSW16 (1 << 12) #define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) #define MCTL_CR_CHANNEL_MASK (1 << 19) #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) #define MCTL_CR_UNKNOWN (0x4 << 20) @@ -198,4 +198,6 @@ struct sunxi_mctl_ctl_reg { #define MCTL_MR2 0x18 /* CWL=8 */ #define MCTL_MR3 0x0 +#define DRAM_TYPE_DDR3 3 +#define DRAM_TYPE_LPDDR3 7 #endif /* _SUNXI_DRAM_SUN8I_A83T_H */
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet 1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. DRAM_TYPE=3 for DDR3 and 7 for LPDDR3 will passed to SYS_EXTRA_OPTIONS from respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> --- arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c | 11 ++++++++++- arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 4 +++- 2 files changed, 13 insertions(+), 2 deletions(-)