| Message ID | 1450580409-6387-1-git-send-email-marex@denx.de |
|---|---|
| State | Accepted |
| Delegated to: | Marek Vasut |
| Headers | show |
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote: > The L2 cache was never enabled in the v7_outer_cache_enable(), fix > this and enable the L2 cache. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Chin Liang See <clsee@altera.com> > --- > arch/arm/mach-socfpga/misc.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > V2: Add v7_outer_cache_disable() as suggested by SR . > Acked-by: Chin Liang See <clsee@altera.com> Thanks Chin Liang
On Monday, December 21, 2015 at 10:54:22 AM, Chin Liang See wrote: > On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote: > > The L2 cache was never enabled in the v7_outer_cache_enable(), fix > > this and enable the L2 cache. > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > Cc: Chin Liang See <clsee@altera.com> > > --- > > > > arch/arm/mach-socfpga/misc.c | 13 +++++++++++-- > > 1 file changed, 11 insertions(+), 2 deletions(-) > > > > V2: Add v7_outer_cache_disable() as suggested by SR . > > Acked-by: Chin Liang See <clsee@altera.com> Applied, thanks. Best regards, Marek Vasut
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index b110f5b..a54d2b9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /*
The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- arch/arm/mach-socfpga/misc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) V2: Add v7_outer_cache_disable() as suggested by SR .