| Message ID | 1441705084-5503-2-git-send-email-thierry.reding@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Warren |
| Headers | show |
On Tue, Sep 08, 2015 at 03:58:38PM +0000, Tom Warren wrote: > Thierry, > > > -----Original Message----- > > From: Thierry Reding [mailto:thierry.reding@gmail.com] > > Sent: Tuesday, September 08, 2015 2:38 AM > > To: Tom Warren > > Cc: Nicolas Chauvet; u-boot@lists.denx.de > > Subject: [PATCH 2/2] ARM: tegra114: Clear IDDQ when enabling PLLC > > > > From: Thierry Reding <treding@nvidia.com> > > > > Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and > > warns about it verbosely, so while this seems to work fine, fix it up according to > > the programming guidelines provided in the Tegra K1 TRM (v02p), Section > > 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't > > contain this information, but the programming of PLLC is the same on Tegra114 > > and Tegra124. > Do we need this for T210, too? A quick glance at the TRM shows IDDQ for PLLA, M, C, U, P, D. I suspect that we might need this for Tegra210 as well, though I haven't encountered the warning yet. That said, I think this is a fairly new warning, though the code's been in the kernel since essentially forever, so it could be that I just haven't encountered it on Tegra210 because I haven't tested with the right U-Boot/kernel combination. On that note, any ideas on what could've triggered this? I know there were a couple of changes to the Tegra clock code in U-Boot recently, but I don't remember seeing anything suspicious. Thierry > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > arch/arm/include/asm/arch-tegra114/clock.h | 3 +++ > > arch/arm/mach-tegra/tegra114/clock.c | 5 +++++ > > 2 files changed, 8 insertions(+) > > > > diff --git a/arch/arm/include/asm/arch-tegra114/clock.h > > b/arch/arm/include/asm/arch-tegra114/clock.h > > index abbefcd0e456..9bee39778747 100644 > > --- a/arch/arm/include/asm/arch-tegra114/clock.h > > +++ b/arch/arm/include/asm/arch-tegra114/clock.h > > @@ -25,4 +25,7 @@ > > #define OSC_FREQ_SHIFT 28 > > #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) > > > > +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ > > +#define PLLC_IDDQ (1 << 26) > > + > > #endif /* _TEGRA114_CLOCK_H_ */ > > diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach- > > tegra/tegra114/clock.c > > index cec843b27df7..e6ef873c8dc4 100644 > > --- a/arch/arm/mach-tegra/tegra114/clock.c > > +++ b/arch/arm/mach-tegra/tegra114/clock.c > > @@ -629,6 +629,11 @@ void clock_early_init(void) > > > > tegra30_set_up_pllp(); > > > > + /* clear IDDQ before accessing any other PLLC registers */ > > + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; > > + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, > > PLLC_IDDQ); > > + udelay(2); > > + > > /* > > * PLLC output frequency set to 600Mhz > > * PLLD output frequency set to 925Mhz > > -- > > 2.5.0 >
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h index abbefcd0e456..9bee39778747 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/include/asm/arch-tegra114/clock.h @@ -25,4 +25,7 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + #endif /* _TEGRA114_CLOCK_H_ */ diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index cec843b27df7..e6ef873c8dc4 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -629,6 +629,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz