| Message ID | 1439668968-3882-12-git-send-email-hdegoede@redhat.com |
|---|---|
| State | Accepted |
| Delegated to: | Hans de Goede |
| Headers | show |
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote: > Other then having a few less chip-select lines the nand controller > on sun4i, sun5i and sun7i is identical. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > board/sunxi/board.c | 12 +++++++++--- > drivers/mtd/nand/Kconfig | 4 ++-- > 2 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c > index 1ebd0a4..d411e96 100644 > --- a/board/sunxi/board.c > +++ b/board/sunxi/board.c > @@ -112,13 +112,19 @@ int dram_init(void) > static void nand_pinmux_setup(void) > { > unsigned int pin; > - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) > - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); > > - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) > + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) This looks to have added GPC(7) to all platforms, was that intentional? Ian.
Hi, On 17-08-15 10:29, Ian Campbell wrote: > On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote: >> Other then having a few less chip-select lines the nand controller >> on sun4i, sun5i and sun7i is identical. >> >> Signed-off-by: Hans de Goede <hdegoede@redhat.com> >> --- >> board/sunxi/board.c | 12 +++++++++--- >> drivers/mtd/nand/Kconfig | 4 ++-- >> 2 files changed, 11 insertions(+), 5 deletions(-) >> >> diff --git a/board/sunxi/board.c b/board/sunxi/board.c >> index 1ebd0a4..d411e96 100644 >> --- a/board/sunxi/board.c >> +++ b/board/sunxi/board.c >> @@ -112,13 +112,19 @@ int dram_init(void) >> static void nand_pinmux_setup(void) >> { >> unsigned int pin; >> - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) >> - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); >> >> - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) >> + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) > > This looks to have added GPC(7) to all platforms, was that intentional? Yes, as GPC7 is a nand pin on all platforms, no idea why the original code was skipping it. I should probably mention this in the commit msg though. Regards, Hans
On Mon, 2015-08-17 at 10:31 +0200, Hans de Goede wrote: > Hi, > > On 17-08-15 10:29, Ian Campbell wrote: > > On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote: > > > Other then having a few less chip-select lines the nand > > > controller > > > on sun4i, sun5i and sun7i is identical. > > > > > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > > > --- > > > board/sunxi/board.c | 12 +++++++++--- > > > drivers/mtd/nand/Kconfig | 4 ++-- > > > 2 files changed, 11 insertions(+), 5 deletions(-) > > > > > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c > > > index 1ebd0a4..d411e96 100644 > > > --- a/board/sunxi/board.c > > > +++ b/board/sunxi/board.c > > > @@ -112,13 +112,19 @@ int dram_init(void) > > > static void nand_pinmux_setup(void) > > > { > > > unsigned int pin; > > > - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) > > > - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); > > > > > > - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) > > > + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) > > > > This looks to have added GPC(7) to all platforms, was that > > intentional? > > Yes, as GPC7 is a nand pin on all platforms, no idea why the original > code was skipping it. I should probably mention this in the commit > msg though. Please, then: Acked-by: Ian Campbell <ijc@hellion.org.uk>
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1ebd0a4..d411e96 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -112,13 +112,19 @@ int dram_init(void) static void nand_pinmux_setup(void) { unsigned int pin; - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I + for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#endif + /* sun4i / sun7i do have a PC23, but it is not used for nand, + * only sun7i has a PC24 */ +#ifdef CONFIG_MACH_SUN7I sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +#endif } static void nand_clock_setup(void) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 8a3fae5..e3cbc31 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -86,8 +86,8 @@ config SPL_NAND_DENALI for use on SPL. config SPL_NAND_SUNXI - bool "Support for NAND on Allwinner A20 in SPL" - depends on MACH_SUN7I + bool "Support for NAND on Allwinner SoCs in SPL" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I select SYS_NAND_SELF_INIT ---help--- Enable support for NAND. This option allows SPL to read from
Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- board/sunxi/board.c | 12 +++++++++--- drivers/mtd/nand/Kconfig | 4 ++-- 2 files changed, 11 insertions(+), 5 deletions(-)