diff mbox

[U-Boot,1/7] arm: lpc32xx: mux: add missing registers

Message ID 1438018660-19858-2-git-send-email-slemieux.tyco@gmail.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Sylvain Lemieux July 27, 2015, 5:37 p.m. UTC
From: Sylvain Lemieux <slemieux@tycoint.com>

Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
---
 arch/arm/include/asm/arch-lpc32xx/cpu.h |  2 +-
 arch/arm/include/asm/arch-lpc32xx/mux.h | 17 +++++++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)

Comments

Tom Rini Aug. 13, 2015, 1:20 p.m. UTC | #1
On Mon, Jul 27, 2015 at 01:37:34PM -0400, slemieux.tyco@gmail.com wrote:

> From: Sylvain Lemieux <slemieux@tycoint.com>
> 
> Add missing registers in struct definition.
> Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).
> 
> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>

Applied to u-boot/master, thanks!
LEMIEUX, SYLVAIN Aug. 17, 2015, 11:34 a.m. UTC | #2
Hi Tom,

I resynchronize the master branch this morning,
and only patch 7/7 of the series appear in u-boot/master;

Is it possible that patch 1/7 to 6/7 were not applied?

For your convenience this is a list of links to patchwork:
* http://patchwork.ozlabs.org/patch/500510/
* http://patchwork.ozlabs.org/patch/500512/
* http://patchwork.ozlabs.org/patch/500513/
* http://patchwork.ozlabs.org/patch/500511/
* http://patchwork.ozlabs.org/patch/500514/
* http://patchwork.ozlabs.org/patch/500515/


Sylvain Lemieux

> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Tom Rini
> Sent: 13-Aug-15 9:20 AM
>
> On Mon, Jul 27, 2015 at 01:37:34PM -0400, slemieux.tyco@gmail.com wrote:
>
> > From: Sylvain Lemieux <slemieux@tycoint.com>
> >
> > Add missing registers in struct definition.
> > Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).
> >
> > Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
>
> Applied to u-boot/master, thanks!
>
> --
> Tom
Tom Rini Aug. 17, 2015, 12:14 p.m. UTC | #3
On Mon, Aug 17, 2015 at 11:34:59AM +0000, LEMIEUX, SYLVAIN wrote:

> Hi Tom,
> 
> I resynchronize the master branch this morning,
> and only patch 7/7 of the series appear in u-boot/master;
> 
> Is it possible that patch 1/7 to 6/7 were not applied?
> 
> For your convenience this is a list of links to patchwork:
> * http://patchwork.ozlabs.org/patch/500510/
> * http://patchwork.ozlabs.org/patch/500512/
> * http://patchwork.ozlabs.org/patch/500513/
> * http://patchwork.ozlabs.org/patch/500511/
> * http://patchwork.ozlabs.org/patch/500514/
> * http://patchwork.ozlabs.org/patch/500515/

Oops, I dropped them by accident doing some re-ordering, fixed now.
Sorry!
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 0b5dca1..0de894b 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -27,7 +27,7 @@ 
 #define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
 #define RTC_BASE	0x40024000	/* RTC registers base               */
 #define GPIO_BASE	0x40028000	/* GPIO registers base              */
-#define MUX_BASE	0x40028100	/* MUX registers base               */
+#define MUX_BASE	0x40028000	/* MUX registers base               */
 #define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
 #define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
 #define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h
index dc1b5bc..665ea3f 100644
--- a/arch/arm/include/asm/arch-lpc32xx/mux.h
+++ b/arch/arm/include/asm/arch-lpc32xx/mux.h
@@ -12,7 +12,24 @@ 
  */
 
 struct mux_regs {
+	u32 reserved1[10];
+	u32 p2_mux_set;
+	u32 p2_mux_clr;
+	u32 p2_mux_state;
+	u32 reserved2[51];
 	u32 p_mux_set;
 	u32 p_mux_clr;
 	u32 p_mux_state;
+	u32 reserved3;
+	u32 p3_mux_set;
+	u32 p3_mux_clr;
+	u32 p3_mux_state;
+	u32 reserved4;
+	u32 p0_mux_set;
+	u32 p0_mux_clr;
+	u32 p0_mux_state;
+	u32 reserved5;
+	u32 p1_mux_set;
+	u32 p1_mux_clr;
+	u32 p1_mux_state;
 };