| Message ID | 1437391715-1344-16-git-send-email-Peng.Fan@freescale.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefano Babic |
| Headers | show |
On 20/07/2015 13:28, Peng Fan wrote: > 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. > 2. Support SPL > 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default > supports sd for usdhc2, but can do hardware rework to make usdhc2 support > emmc. > > Boot Log: > U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) > reading u-boot.img > reading u-boot.img > > U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) > > CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) > CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 > - invalid sensor device > Reset cause: POR > Board: MX6UL 14x14 EVK > I2C: ready > DRAM: 512 MiB > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Net: CPU Net Initialization Failed > No ethernet found. > Hit any key to stop autoboot: 0 > > Signed-off-by: Peng Fan <Peng.Fan@freescale.com> > --- > > Changes v3: > none > > Changes v2: > Add SPL support > More commit msg for CONFIG_MX6UL_14X14_EVK_EMMC_REWORK. > > arch/arm/Kconfig | 8 + > board/freescale/mx6ul_14x14_evk/Kconfig | 15 + > board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 + > board/freescale/mx6ul_14x14_evk/Makefile | 6 + > board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++++++++++++ > configs/mx6ul_14x14_evk_defconfig | 4 + > include/configs/mx6ul_14x14_evk.h | 227 ++++++++ > 7 files changed, 902 insertions(+) > create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig > create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS > create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile > create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c > create mode 100644 configs/mx6ul_14x14_evk_defconfig > create mode 100644 include/configs/mx6ul_14x14_evk.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 9908b43..14a622e 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -575,6 +575,13 @@ config TARGET_MX6SXSABRESD > select DM > select DM_THERMAL > > +config TARGET_MX6UL_14X14_EVK > + bool "Support mx6ul_14x14_evk" > + select CPU_V7 > + select DM > + select DM_THERMAL > + select SUPPORT_SPL > + > config TARGET_GW_VENTANA > bool "Support gw_ventana" > select CPU_V7 > @@ -920,6 +927,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" > source "board/freescale/mx6sabresd/Kconfig" > source "board/freescale/mx6slevk/Kconfig" > source "board/freescale/mx6sxsabresd/Kconfig" > +source "board/freescale/mx6ul_14x14_evk/Kconfig" > source "board/freescale/vf610twr/Kconfig" > source "board/gateworks/gw_ventana/Kconfig" > source "board/genesi/mx51_efikamx/Kconfig" > diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig > new file mode 100644 > index 0000000..393aca6 > --- /dev/null > +++ b/board/freescale/mx6ul_14x14_evk/Kconfig > @@ -0,0 +1,15 @@ > +if TARGET_MX6UL_14X14_EVK > + > +config SYS_BOARD > + default "mx6ul_14x14_evk" > + > +config SYS_VENDOR > + default "freescale" > + > +config SYS_SOC > + default "mx6" > + > +config SYS_CONFIG_NAME > + default "mx6ul_14x14_evk" > + > +endif > diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS > new file mode 100644 > index 0000000..611feca > --- /dev/null > +++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS > @@ -0,0 +1,6 @@ > +MX6ULEVK BOARD > +M: Peng Fan <Peng.Fan@freescale.com> > +S: Maintained > +F: board/freescale/mx6ul_14x14_evk/ > +F: include/configs/mx6ul_14x14_evk.h > +F: configs/mx6ul_14x14_evk_defconfig > diff --git a/board/freescale/mx6ul_14x14_evk/Makefile b/board/freescale/mx6ul_14x14_evk/Makefile > new file mode 100644 > index 0000000..61f6778 > --- /dev/null > +++ b/board/freescale/mx6ul_14x14_evk/Makefile > @@ -0,0 +1,6 @@ > +# (C) Copyright 2015 Freescale Semiconductor, Inc. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y := mx6ul_14x14_evk.o > diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c > new file mode 100644 > index 0000000..8f712cb > --- /dev/null > +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c > @@ -0,0 +1,636 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <asm/arch/clock.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/crm_regs.h> > +#include <asm/arch/mx6ul_pins.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/gpio.h> > +#include <asm/imx-common/iomux-v3.h> > +#include <asm/imx-common/boot_mode.h> > +#include <asm/imx-common/mxc_i2c.h> > +#include <asm/io.h> > +#include <common.h> > +#include <fsl_esdhc.h> > +#include <i2c.h> > +#include <linux/sizes.h> > +#include <mmc.h> > +#include <usb.h> > +#include <usb/ehci-fsl.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ > + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ > + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ > + PAD_CTL_ODE) > + > +#define IOX_SDI IMX_GPIO_NR(5, 10) > +#define IOX_STCP IMX_GPIO_NR(5, 7) > +#define IOX_SHCP IMX_GPIO_NR(5, 11) > +#define IOX_OE IMX_GPIO_NR(5, 18) > + > +static iomux_v3_cfg_t const iox_pads[] = { > + /* IOX_SDI */ > + MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* IOX_SHCP */ > + MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* IOX_STCP */ > + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* IOX_nOE */ > + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +/* > + * HDMI_nRST --> Q0 > + * ENET1_nRST --> Q1 > + * ENET2_nRST --> Q2 > + * CAN1_2_STBY --> Q3 > + * BT_nPWD --> Q4 > + * CSI_RST --> Q5 > + * CSI_PWDN --> Q6 > + * LCD_nPWREN --> Q7 > + */ > +enum qn { > + HDMI_NRST, > + ENET1_NRST, > + ENET2_NRST, > + CAN1_2_STBY, > + BT_NPWD, > + CSI_RST, > + CSI_PWDN, > + LCD_NPWREN, > +}; > + > +enum qn_func { > + qn_reset, > + qn_enable, > + qn_disable, > +}; > + > +enum qn_level { > + qn_low = 0, > + qn_high = 1, > +}; > + > +static enum qn_level seq[3][2] = { > + {0, 1}, {1, 1}, {0, 0} > +}; > + > +static enum qn_func qn_output[8] = { > + qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, > + qn_disable, qn_enable > +}; > + > +static void iox74lv_init(void) > +{ > + int i; > + > + gpio_direction_output(IOX_OE, 0); > + > + for (i = 7; i >= 0; i--) { > + gpio_direction_output(IOX_SHCP, 0); > + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); > + udelay(500); > + gpio_direction_output(IOX_SHCP, 1); > + udelay(500); > + } > + > + gpio_direction_output(IOX_STCP, 0); > + udelay(500); > + /* > + * shift register will be output to pins > + */ > + gpio_direction_output(IOX_STCP, 1); > + > + for (i = 7; i >= 0; i--) { > + gpio_direction_output(IOX_SHCP, 0); > + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); > + udelay(500); > + gpio_direction_output(IOX_SHCP, 1); > + udelay(500); > + } > + gpio_direction_output(IOX_STCP, 0); > + udelay(500); > + /* > + * shift register will be output to pins > + */ > + gpio_direction_output(IOX_STCP, 1); > + > + gpio_direction_output(IOX_OE, 1); > +}; > + > +void iox74lv_set(int index) > +{ > + int i; > + > + gpio_direction_output(IOX_OE, 0); > + > + for (i = 7; i >= 0; i--) { > + gpio_direction_output(IOX_SHCP, 0); > + > + if (i == index) > + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); > + else > + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); > + udelay(500); > + gpio_direction_output(IOX_SHCP, 1); > + udelay(500); > + } > + > + gpio_direction_output(IOX_STCP, 0); > + udelay(500); > + /* > + * shift register will be output to pins > + */ > + gpio_direction_output(IOX_STCP, 1); > + > + for (i = 7; i >= 0; i--) { > + gpio_direction_output(IOX_SHCP, 0); > + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); > + udelay(500); > + gpio_direction_output(IOX_SHCP, 1); > + udelay(500); > + } > + > + gpio_direction_output(IOX_STCP, 0); > + udelay(500); > + /* > + * shift register will be output to pins > + */ > + gpio_direction_output(IOX_STCP, 1); > + > + gpio_direction_output(IOX_OE, 1); > +}; > + > +#ifdef CONFIG_SYS_I2C_MXC > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > +/* I2C1 for PMIC and EEPROM */ > +struct i2c_pads_info i2c_pad_info1 = { > + .scl = { > + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, > + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, > + .gp = IMX_GPIO_NR(1, 28), > + }, > + .sda = { > + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, > + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, > + .gp = IMX_GPIO_NR(1, 29), > + }, > +}; > +#endif > + > +int dram_init(void) > +{ > + gd->ram_size = PHYS_SDRAM_SIZE; > + > + return 0; > +} > + > +static iomux_v3_cfg_t const uart1_pads[] = { > + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const usdhc1_pads[] = { > + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + > + /* VSELECT */ > + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + /* CD */ > + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* RST_B */ > + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +/* > + * mx6ul_14x14_evk board default supports sd card. If want to use > + * EMMC, need to do board rework for sd2. > + * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support > + * emmc, need to define this macro. > + */ > +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) > +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { > + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + > + /* > + * RST_B > + */ > + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > +#else > +static iomux_v3_cfg_t const usdhc2_pads[] = { > + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const usdhc2_cd_pads[] = { > + /* > + * The evk board uses DAT3 to detect CD card plugin, > + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. > + */ > + MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | > + MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), > +}; > +#endif > + > +static void setup_iomux_uart(void) > +{ > + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); > +} > + > +#ifdef CONFIG_FSL_QSPI > + > +#define QSPI_PAD_CTRL1 \ > + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ > + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) > + > +static iomux_v3_cfg_t const quadspi_pads[] = { > + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), > + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), > + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), > + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), > + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), > + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), > +}; > + > +int board_qspi_init(void) > +{ > + /* Set the iomux */ > + imx_iomux_v3_setup_multiple_pads(quadspi_pads, > + ARRAY_SIZE(quadspi_pads)); > + /* Set the clock */ > + enable_qspi_clk(0); > + > + return 0; > +} > +#endif > + > +#ifdef CONFIG_FSL_ESDHC > +static struct fsl_esdhc_cfg usdhc_cfg[2] = { > + {USDHC1_BASE_ADDR, 0, 4}, > +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) > + {USDHC2_BASE_ADDR, 0, 8}, > +#else > + {USDHC2_BASE_ADDR, 0, 4}, > +#endif > +}; > + > +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) > +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) > +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; > + int ret = 0; > + > + switch (cfg->esdhc_base) { > + case USDHC1_BASE_ADDR: > + ret = !gpio_get_value(USDHC1_CD_GPIO); > + break; > + case USDHC2_BASE_ADDR: > +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) > + ret = 1; > +#else > + imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, > + ARRAY_SIZE(usdhc2_cd_pads)); > + gpio_direction_input(USDHC2_CD_GPIO); > + > + /* > + * Since it is the DAT3 pin, this pin is pulled to > + * low voltage if no card > + */ > + ret = gpio_get_value(USDHC2_CD_GPIO); > + > + imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, > + ARRAY_SIZE(usdhc2_dat3_pads)); > +#endif > + break; > + } > + > + return ret; > +} > + > +int board_mmc_init(bd_t *bis) > +{ > +#ifdef CONFIG_SPL_BUILD > +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) > + imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, > + ARRAY_SIZE(usdhc2_emmc_pads)); > +#else > + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); > +#endif > + gpio_direction_output(USDHC2_PWR_GPIO, 0); > + udelay(500); > + gpio_direction_output(USDHC2_PWR_GPIO, 1); > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); > + return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); > +#else > + int i, ret; > + > + /* > + * According to the board_mmc_init() the following map is done: > + * (U-boot device node) (Physical Port) > + * mmc0 USDHC1 > + * mmc1 USDHC2 > + */ > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > + switch (i) { > + case 0: > + imx_iomux_v3_setup_multiple_pads( > + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); > + gpio_direction_input(USDHC1_CD_GPIO); > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > + > + gpio_direction_output(USDHC1_PWR_GPIO, 0); > + udelay(500); > + gpio_direction_output(USDHC1_PWR_GPIO, 1); > + break; > + case 1: > +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) > + imx_iomux_v3_setup_multiple_pads( > + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); > +#else > + imx_iomux_v3_setup_multiple_pads( > + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); > +#endif > + gpio_direction_output(USDHC2_PWR_GPIO, 0); > + udelay(500); > + gpio_direction_output(USDHC2_PWR_GPIO, 1); > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); > + break; > + default: > + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); > + return -EINVAL; > + } > + > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); > + if (ret) { > + printf("Warning: failed to initialize mmc dev %d\n", i); > + return ret; > + } > + } > +#endif > + return 0; > +} > +#endif > + > +#ifdef CONFIG_USB_EHCI_MX6 > +#define USB_OTHERREGS_OFFSET 0x800 > +#define UCTRL_PWR_POL (1 << 9) > + > +static iomux_v3_cfg_t const usb_otg_pads[] = { > + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +/* At default the 3v3 enables the MIC2026 for VBUS power */ > +static void setup_usb(void) > +{ > + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, > + ARRAY_SIZE(usb_otg_pads)); > +} > + > +int board_usb_phy_mode(int port) > +{ > + if (port == 1) > + return USB_INIT_HOST; > + else > + return usb_phy_mode(port); > +} > + > +int board_ehci_hcd_init(int port) > +{ > + u32 *usbnc_usb_ctrl; > + > + if (port > 1) > + return -EINVAL; > + > + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + > + port * 4); > + > + /* Set Power polarity */ > + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); > + > + return 0; > +} > +#endif > + > +int board_early_init_f(void) > +{ > + setup_iomux_uart(); > + > + return 0; > +} > + > +int board_init(void) > +{ > + /* Address of boot parameters */ > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + > + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); > + > + iox74lv_init(); > + > +#ifdef CONFIG_SYS_I2C_MXC > + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); > +#endif > + > +#ifdef CONFIG_USB_EHCI_MX6 > + setup_usb(); > +#endif > + > +#ifdef CONFIG_FSL_QSPI > + board_qspi_init(); > +#endif > + > + return 0; > +} > + > +#ifdef CONFIG_CMD_BMODE > +static const struct boot_mode board_boot_modes[] = { > + /* 4 bit bus width */ > + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, > + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, > + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, > + {NULL, 0}, > +}; > +#endif > + > +int board_late_init(void) > +{ > +#ifdef CONFIG_CMD_BMODE > + add_board_boot_modes(board_boot_modes); > +#endif > + > + return 0; > +} > + > +u32 get_board_rev(void) > +{ > + return get_cpu_rev(); > +} > + > +int checkboard(void) > +{ > + puts("Board: MX6UL 14x14 EVK\n"); > + > + return 0; > +} > + > +#ifdef CONFIG_SPL_BUILD > +#include <libfdt.h> > +#include <spl.h> > +#include <asm/arch/mx6-ddr.h> > + > +const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { > + .dram_dqm0 = 0x00000030, > + .dram_dqm1 = 0x00000030, > + .dram_ras = 0x00000030, > + .dram_cas = 0x00000030, > + .dram_odt0 = 0x00000030, > + .dram_odt1 = 0x00000030, > + .dram_sdba2 = 0x00000000, > + .dram_sdclk_0 = 0x00000008, > + .dram_sdqs0 = 0x00000038, > + .dram_sdqs1 = 0x00000030, > + .dram_reset = 0x00000030, > +}; > + > +const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { > + .grp_addds = 0x00000030, > + .grp_ddrmode_ctl = 0x00020000, > + .grp_b0ds = 0x00000030, > + .grp_ctlds = 0x00000030, > + .grp_b1ds = 0x00000030, > + .grp_ddrpke = 0x00000000, > + .grp_ddrmode = 0x00020000, > + .grp_ddr_type = 0x000c0000, > +}; > + > +const struct mx6_mmdc_calibration mx6_mmcd_calib = { > + .p0_mpwldectrl0 = 0x00070007, > + .p0_mpdgctrl0 = 0x41490145, > + .p0_mprddlctl = 0x40404546, > + .p0_mpwrdlctl = 0x4040524D, > +}; > + > +static struct mx6_ddr3_cfg mem_ddr = { > + .mem_speed = 800, > + .density = 4, > + .width = 16, > + .banks = 8, > + .rowaddr = 15, > + .coladdr = 10, > + .pagesz = 2, > + .trcd = 1375, > + .trcmin = 4875, > + .trasmin = 3500, > +}; > + > +static void ccgr_init(void) > +{ > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + > + writel(0xFFFFFFFF, &ccm->CCGR0); > + writel(0xFFFFFFFF, &ccm->CCGR1); > + writel(0xFFFFFFFF, &ccm->CCGR2); > + writel(0xFFFFFFFF, &ccm->CCGR3); > + writel(0xFFFFFFFF, &ccm->CCGR4); > + writel(0xFFFFFFFF, &ccm->CCGR5); > + writel(0xFFFFFFFF, &ccm->CCGR6); > + writel(0xFFFFFFFF, &ccm->CCGR7); > +} > + > +static void spl_dram_init(void) > +{ > + struct mx6_ddr_sysinfo sysinfo = { > + .dsize = 0, > + .cs_density = 20, > + .ncs = 1, > + .cs1_mirror = 0, > + .rtt_wr = 2, > + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ > + .walat = 1, /* Write additional latency */ > + .ralat = 5, /* Read additional latency */ > + .mif3_mode = 3, /* Command prediction working mode */ > + .bi_on = 1, /* Bank interleaving enabled */ > + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ > + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ > + }; > + > + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); > + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); > +} > + > +void board_init_f(ulong dummy) > +{ > + /* setup AIPS and disable watchdog */ > + arch_cpu_init(); > + > + ccgr_init(); > + > + /* iomux and setup of i2c */ > + board_early_init_f(); > + > + /* setup GP timer */ > + timer_init(); > + > + /* UART clocks enabled and gd valid - init serial console */ > + preloader_console_init(); > + > + /* DDR initialization */ > + spl_dram_init(); > + > + /* Clear the BSS. */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + /* load/boot image from boot device */ > + board_init_r(NULL, 0); > +} > + > +void reset_cpu(ulong addr) > +{ > +} > +#endif > diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig > new file mode 100644 > index 0000000..b6eefaf > --- /dev/null > +++ b/configs/mx6ul_14x14_evk_defconfig > @@ -0,0 +1,4 @@ > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL" > +CONFIG_ARM=y > +CONFIG_TARGET_MX6UL_14X14_EVK=y > +CONFIG_SPL=y > diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h > new file mode 100644 > index 0000000..436b022 > --- /dev/null > +++ b/include/configs/mx6ul_14x14_evk.h > @@ -0,0 +1,227 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#ifndef __MX6UL_14X14_EVK_CONFIG_H > +#define __MX6UL_14X14_EVK_CONFIG_H > + > + > +#include <asm/arch/imx-regs.h> > +#include <linux/sizes.h> > +#include "mx6_common.h" > +#include <asm/imx-common/gpio.h> > + > +/* SPL options */ > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_MMC_SUPPORT > +#define CONFIG_SPL_FAT_SUPPORT > +#include "imx6_spl.h" > + > +#define CONFIG_MX6 > +#define CONFIG_ROM_UNIFIED_SECTIONS > +#define CONFIG_SYS_GENERIC_BOARD > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) > + > +#define CONFIG_BOARD_EARLY_INIT_F > +#define CONFIG_BOARD_LATE_INIT > + > +#define CONFIG_MXC_UART > +#define CONFIG_MXC_UART_BASE UART1_BASE > + > +#define CONFIG_CMD_FUSE > +#ifdef CONFIG_CMD_FUSE > +#define CONFIG_MXC_OCOTP > +#endif > + > +/* MMC Configs */ > +#ifdef CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR > + > +/* NAND pin conflicts with usdhc2 */ > +#ifdef CONFIG_NAND_MXS > +#define CONFIG_SYS_FSL_USDHC_NUM 1 > +#else > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > +#endif > + > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ > +#endif > + > +#undef CONFIG_BOOTM_NETBSD > +#undef CONFIG_BOOTM_PLAN9 > +#undef CONFIG_BOOTM_RTEMS > + > +#undef CONFIG_CMD_EXPORTENV > +#undef CONFIG_CMD_IMPORTENV > + > +/* I2C configs */ > +#define CONFIG_CMD_I2C > +#ifdef CONFIG_CMD_I2C > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_MXC > +#define CONFIG_SYS_I2C_SPEED 100000 > +#endif > + > +#define PHYS_SDRAM_SIZE SZ_512M > + > +#undef CONFIG_CMD_IMLS > + > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "script=boot.scr\0" \ > + "image=zImage\0" \ > + "console=ttymxc0\0" \ > + "fdt_high=0xffffffff\0" \ > + "initrd_high=0xffffffff\0" \ > + "fdt_file=imx6ul-14x14-evk.dtb\0" \ > + "fdt_addr=0x83000000\0" \ > + "boot_fdt=try\0" \ > + "ip_dyn=yes\0" \ > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + "mmcautodetect=yes\0" \ > + "mmcargs=setenv bootargs console=${console},${baudrate} " \ > + "root=${mmcroot}\0" \ > + "loadbootscript=" \ > + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ > + "bootscript=echo Running bootscript from mmc ...; " \ > + "source\0" \ > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if run loadfdt; then " \ > + "bootz ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "if test ${boot_fdt} = try; then " \ > + "bootz; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "fi; " \ > + "else " \ > + "bootz; " \ > + "fi;\0" \ > + "netargs=setenv bootargs console=${console},${baudrate} " \ > + "root=/dev/nfs " \ > + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ > + "netboot=echo Booting from net ...; " \ > + "run netargs; " \ > + "if test ${ip_dyn} = yes; then " \ > + "setenv get_cmd dhcp; " \ > + "else " \ > + "setenv get_cmd tftp; " \ > + "fi; " \ > + "${get_cmd} ${image}; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ > + "bootz ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "if test ${boot_fdt} = try; then " \ > + "bootz; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "fi; " \ > + "else " \ > + "bootz; " \ > + "fi;\0" > + > +#define CONFIG_BOOTCOMMAND \ > + "mmc dev ${mmcdev};" \ > + "mmc dev ${mmcdev}; if mmc rescan; then " \ > + "if run loadbootscript; then " \ > + "run bootscript; " \ > + "else " \ > + "if run loadimage; then " \ > + "run mmcboot; " \ > + "else run netboot; " \ > + "fi; " \ > + "fi; " \ > + "else run netboot; fi" > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_PROMPT "=> " > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +#define CONFIG_CMD_MEMTEST > +#define CONFIG_SYS_MEMTEST_START 0x80000000 > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > +#define CONFIG_SYS_HZ 1000 > + > +#define CONFIG_CMDLINE_EDITING > +#define CONFIG_STACKSIZE SZ_128K > + > +/* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > + > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > + > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* FLASH and environment organization */ > +#define CONFIG_SYS_NO_FLASH > + > +#define CONFIG_ENV_SIZE SZ_8K > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_ENV_OFFSET (8 * SZ_64K) > +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ > +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ > +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ > + > +#define CONFIG_OF_LIBFDT > +#define CONFIG_CMD_BOOTZ > +#define CONFIG_CMD_BMODE > + > +#ifndef CONFIG_SYS_DCACHE_OFF > +#define CONFIG_CMD_CACHE > +#endif > + > +#define CONFIG_FSL_QSPI > +#ifdef CONFIG_FSL_QSPI > +#define CONFIG_CMD_SF > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_STMICRO > +#define CONFIG_SPI_FLASH_BAR > +#define CONFIG_SF_DEFAULT_BUS 0 > +#define CONFIG_SF_DEFAULT_CS 0 > +#define CONFIG_SF_DEFAULT_SPEED 40000000 > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 > +#define FSL_QSPI_FLASH_NUM 1 > +#define FSL_QSPI_FLASH_SIZE SZ_32M > +#endif > + > +/* USB Configs */ > +#define CONFIG_CMD_USB > +#ifdef CONFIG_CMD_USB > +#define CONFIG_USB_EHCI > +#define CONFIG_USB_EHCI_MX6 > +#define CONFIG_USB_STORAGE > +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET > +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) > +#define CONFIG_MXC_USB_FLAGS 0 > +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 > +#endif > + > +#define CONFIG_IMX6_THERMAL > + > +#endif > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
Hi Peng, On Mon, Jul 20, 2015 at 8:28 AM, Peng Fan <Peng.Fan@freescale.com> wrote: > 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. > 2. Support SPL > 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default > supports sd for usdhc2, but can do hardware rework to make usdhc2 support > emmc. > > Boot Log: > U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) > reading u-boot.img > reading u-boot.img > > U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) > > CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) > CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 > - invalid sensor device > Reset cause: POR > Board: MX6UL 14x14 EVK > I2C: ready > DRAM: 512 MiB > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Net: CPU Net Initialization Failed > No ethernet found. > Hit any key to stop autoboot: 0 > > Signed-off-by: Peng Fan <Peng.Fan@freescale.com> I am running u-boot-imx tree that has this patch applied, but I am not able to boot from SD card: U-Boot SPL 2015.07-22910-g1c23c1e (Aug 10 2015 - 16:17:50) MMC: no card present spl: mmc init failed with error: -16 ### ERROR ### Please RESET the board ### Any ideas? Regards, Fabio Estevam
Hi Fabio, On Mon, Aug 10, 2015 at 01:22:49PM -0300, Fabio Estevam wrote: >Hi Peng, > >On Mon, Jul 20, 2015 at 8:28 AM, Peng Fan <Peng.Fan@freescale.com> wrote: >> 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. >> 2. Support SPL >> 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default >> supports sd for usdhc2, but can do hardware rework to make usdhc2 support >> emmc. >> >> Boot Log: >> U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) >> reading u-boot.img >> reading u-boot.img >> >> U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) >> >> CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) >> CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 >> - invalid sensor device >> Reset cause: POR >> Board: MX6UL 14x14 EVK >> I2C: ready >> DRAM: 512 MiB >> MMC: FSL_SDHC: 0, FSL_SDHC: 1 >> *** Warning - bad CRC, using default environment >> >> In: serial >> Out: serial >> Err: serial >> Net: CPU Net Initialization Failed >> No ethernet found. >> Hit any key to stop autoboot: 0 >> >> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> > >I am running u-boot-imx tree that has this patch applied, but I am not >able to boot from SD card: > >U-Boot SPL 2015.07-22910-g1c23c1e (Aug 10 2015 - 16:17:50) >MMC: no card present >spl: mmc init failed with error: -16 >### ERROR ### Please RESET the board ### > >Any ideas? Are you using the micro sd slot for boot? Please do not use SD1, the big sd card slot. We only support sd2, the micro sd slot for boot. You can refer to the boot select switch. we have no chance to choose sd1 for boot. Regards, Peng. > >Regards, > >Fabio Estevam
Hi Peng, On Mon, Aug 10, 2015 at 9:13 PM, Peng Fan <b51431@freescale.com> wrote: > Are you using the micro sd slot for boot? Please do not use SD1, the big sd > card slot. We only support sd2, the micro sd slot for boot. > > You can refer to the boot select switch. we have no chance to choose sd1 > for boot. I was using the big SD slot and was not aware of this limitation. Will try to boot from the micro SD slot instead. Thanks, Fabio Estevam
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9908b43..14a622e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -575,6 +575,13 @@ config TARGET_MX6SXSABRESD select DM select DM_THERMAL +config TARGET_MX6UL_14X14_EVK + bool "Support mx6ul_14x14_evk" + select CPU_V7 + select DM + select DM_THERMAL + select SUPPORT_SPL + config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7 @@ -920,6 +927,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig new file mode 100644 index 0000000..393aca6 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6UL_14X14_EVK + +config SYS_BOARD + default "mx6ul_14x14_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_evk" + +endif diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS new file mode 100644 index 0000000..611feca --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS @@ -0,0 +1,6 @@ +MX6ULEVK BOARD +M: Peng Fan <Peng.Fan@freescale.com> +S: Maintained +F: board/freescale/mx6ul_14x14_evk/ +F: include/configs/mx6ul_14x14_evk.h +F: configs/mx6ul_14x14_evk_defconfig diff --git a/board/freescale/mx6ul_14x14_evk/Makefile b/board/freescale/mx6ul_14x14_evk/Makefile new file mode 100644 index 0000000..61f6778 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_evk.o diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c new file mode 100644 index 0000000..8f712cb --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -0,0 +1,636 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6ul_pins.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <linux/sizes.h> +#include <mmc.h> +#include <usb.h> +#include <usb/ehci-fsl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define IOX_SDI IMX_GPIO_NR(5, 10) +#define IOX_STCP IMX_GPIO_NR(5, 7) +#define IOX_SHCP IMX_GPIO_NR(5, 11) +#define IOX_OE IMX_GPIO_NR(5, 18) + +static iomux_v3_cfg_t const iox_pads[] = { + /* IOX_SDI */ + MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_SHCP */ + MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_STCP */ + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOX_nOE */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * HDMI_nRST --> Q0 + * ENET1_nRST --> Q1 + * ENET2_nRST --> Q2 + * CAN1_2_STBY --> Q3 + * BT_nPWD --> Q4 + * CSI_RST --> Q5 + * CSI_PWDN --> Q6 + * LCD_nPWREN --> Q7 + */ +enum qn { + HDMI_NRST, + ENET1_NRST, + ENET2_NRST, + CAN1_2_STBY, + BT_NPWD, + CSI_RST, + CSI_PWDN, + LCD_NPWREN, +}; + +enum qn_func { + qn_reset, + qn_enable, + qn_disable, +}; + +enum qn_level { + qn_low = 0, + qn_high = 1, +}; + +static enum qn_level seq[3][2] = { + {0, 1}, {1, 1}, {0, 0} +}; + +static enum qn_func qn_output[8] = { + qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, + qn_disable, qn_enable +}; + +static void iox74lv_init(void) +{ + int i; + + gpio_direction_output(IOX_OE, 0); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + gpio_direction_output(IOX_OE, 1); +}; + +void iox74lv_set(int index) +{ + int i; + + gpio_direction_output(IOX_OE, 0); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + + if (i == index) + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); + else + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + for (i = 7; i >= 0; i--) { + gpio_direction_output(IOX_SHCP, 0); + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); + udelay(500); + gpio_direction_output(IOX_SHCP, 1); + udelay(500); + } + + gpio_direction_output(IOX_STCP, 0); + udelay(500); + /* + * shift register will be output to pins + */ + gpio_direction_output(IOX_STCP, 1); + + gpio_direction_output(IOX_OE, 1); +}; + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, + .gp = IMX_GPIO_NR(1, 28), + }, + .sda = { + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, + .gp = IMX_GPIO_NR(1, 29), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * mx6ul_14x14_evk board default supports sd card. If want to use + * EMMC, need to do board rework for sd2. + * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support + * emmc, need to define this macro. + */ +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* + * RST_B + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_cd_pads[] = { + /* + * The evk board uses DAT3 to detect CD card plugin, + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. + */ + MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | + MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), +}; +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) + {USDHC2_BASE_ADDR, 0, 8}, +#else + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) + ret = 1; +#else + imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, + ARRAY_SIZE(usdhc2_cd_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + + /* + * Since it is the DAT3 pin, this pin is pulled to + * low voltage if no card + */ + ret = gpio_get_value(USDHC2_CD_GPIO); + + imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, + ARRAY_SIZE(usdhc2_dat3_pads)); +#endif + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) + imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, + ARRAY_SIZE(usdhc2_emmc_pads)); +#else + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); +#endif + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); +#else + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: +#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) + imx_iomux_v3_setup_multiple_pads( + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); +#else + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); +#endif + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } +#endif + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* At default the 3v3 enables the MIC2026 for VBUS power */ +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); + + iox74lv_init(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14x14 EVK\n"); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <libfdt.h> +#include <spl.h> +#include <asm/arch/mx6-ddr.h> + +const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig new file mode 100644 index 0000000..b6eefaf --- /dev/null +++ b/configs/mx6ul_14x14_evk_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL" +CONFIG_ARM=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_SPL=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h new file mode 100644 index 0000000..436b022 --- /dev/null +++ b/include/configs/mx6ul_14x14_evk.h @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_EVK_CONFIG_H +#define __MX6UL_14X14_EVK_CONFIG_H + + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" +#include <asm/imx-common/gpio.h> + +/* SPL options */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#include "imx6_spl.h" + +#define CONFIG_MX6 +#define CONFIG_ROM_UNIFIED_SECTIONS +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#endif + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6ul-14x14-evk.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_BMODE + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_FSL_QSPI +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_IMX6_THERMAL + +#endif
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> --- Changes v3: none Changes v2: Add SPL support More commit msg for CONFIG_MX6UL_14X14_EVK_EMMC_REWORK. arch/arm/Kconfig | 8 + board/freescale/mx6ul_14x14_evk/Kconfig | 15 + board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 + board/freescale/mx6ul_14x14_evk/Makefile | 6 + board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++++++++++++ configs/mx6ul_14x14_evk_defconfig | 4 + include/configs/mx6ul_14x14_evk.h | 227 ++++++++ 7 files changed, 902 insertions(+) create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c create mode 100644 configs/mx6ul_14x14_evk_defconfig create mode 100644 include/configs/mx6ul_14x14_evk.h