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[U-Boot,PATCHv3,04/17] arm: socfpga: spl: enable sdram, timer and uart

Message ID 1427752878-18426-5-git-send-email-dinguyen@opensource.altera.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Dinh Nguyen March 30, 2015, 10:01 p.m. UTC 
From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the calls in the spl_board_init to enable SDRAM, timer, and UART.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
---
 arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Marek Vasut April 3, 2015, 1:45 a.m. UTC | #1 
On Tuesday, March 31, 2015 at 12:01:05 AM, dinguyen@opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the calls in the spl_board_init to enable SDRAM, timer, and UART.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> Acked-by: Marek Vasut <marex@denx.de>

Applied to u-boot-socfpga/next , thanks!

Best regards,
Marek Vasut
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Patch

diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 6a8c15d..a4dbe4f 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -144,6 +144,10 @@  void spl_board_init(void)
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
+	socfpga_sdram_enable();
+	socfpga_uart0_enable();
+	socfpga_osc1timer_enable();
+
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);