| Message ID | 1416750195-25318-2-git-send-email-hdegoede@redhat.com |
|---|---|
| State | Accepted |
| Delegated to: | Ian Campbell |
| Headers | show |
On Sun, 2014-11-23 at 14:43 +0100, Hans de Goede wrote: > It turns out that there is a too large spread between boards to handle this > with a default value, turn this into Kconfig options, and set the values > the factory images are using for the Colombus and Mele_M9 boards. > > Note this changes the ZQ default when not overriden through defconfig from > 120 to 123, as that is what most boards seem to actually use. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> With one minor query: > +config DRAM_CLK > + int "sun6i dram clock speed" > + default 312 > + ---help--- > + Set the dram clock speed, valid range 240 - 480, must be a multiple > + of 24. > [...] > diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig > index 40eabce..740b931 100644 > --- a/configs/Mele_M9_defconfig > +++ b/configs/Mele_M9_defconfig > @@ -5,6 +5,8 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb" > +S:CONFIG_ARCH_SUNXI=y > +S:CONFIG_MACH_SUN6I=y > +S:CONFIG_TARGET_MELE_M9=y > ++S:CONFIG_DRAM_CLK=312 You are overriding this to be the default, is that deliberate/necessary? I suspect it's just to keep both or neither of CLK and ZQ explicitly give, which is a fine reason. Ian.
Hi, On 11/25/2014 09:55 AM, Ian Campbell wrote: > On Sun, 2014-11-23 at 14:43 +0100, Hans de Goede wrote: >> It turns out that there is a too large spread between boards to handle this >> with a default value, turn this into Kconfig options, and set the values >> the factory images are using for the Colombus and Mele_M9 boards. >> >> Note this changes the ZQ default when not overriden through defconfig from >> 120 to 123, as that is what most boards seem to actually use. >> >> Signed-off-by: Hans de Goede <hdegoede@redhat.com> > > Acked-by: Ian Campbell <ijc@hellion.org.uk> > > With one minor query: > >> +config DRAM_CLK >> + int "sun6i dram clock speed" >> + default 312 >> + ---help--- >> + Set the dram clock speed, valid range 240 - 480, must be a multiple >> + of 24. >> [...] >> diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig >> index 40eabce..740b931 100644 >> --- a/configs/Mele_M9_defconfig >> +++ b/configs/Mele_M9_defconfig >> @@ -5,6 +5,8 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb" >> +S:CONFIG_ARCH_SUNXI=y >> +S:CONFIG_MACH_SUN6I=y >> +S:CONFIG_TARGET_MELE_M9=y >> ++S:CONFIG_DRAM_CLK=312 > > You are overriding this to be the default, is that deliberate/necessary? > > I suspect it's just to keep both or neither of CLK and ZQ explicitly > give, which is a fine reason. Yes, this is just here to make it easier to see what CLK and ZQ is used without needing to look in the Kconfig, it is also here to make it a better template for other sun6i defconfig-s Regards, Hans
On Sun, 23 Nov 2014 14:43:11 +0100 Hans de Goede <hdegoede@redhat.com> wrote: > It turns out that there is a too large spread between boards to handle this > with a default value, turn this into Kconfig options, and set the values > the factory images are using for the Colombus and Mele_M9 boards. > > Note this changes the ZQ default when not overriden through defconfig from > 120 to 123, as that is what most boards seem to actually use. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> 0x7b (or 123 in the decimal) form is a default reset value in the hardware register (at least on A10/A13/A20 and also on TI Keystone2 hardware). So it indeed makes sense to have it as the default value for u-boot. And also very likely shows that whoever provided the DRAM configurations with this value, did not in fact bother to really configure ZQ to something meaningful :-) In general, if we read the JEDEC booklets, then ZQ calibration is the feature, which allows to improve reliability and increase DRAM clock speeds. The DRAM clock speeds, which are well beyond what the Allwinner A31 boards seem to be using at the moment. I hope that 0x78 value for ZQ on Mele M9 is really there for a reason, and not something like actually 0x7B that got misread from the printed documentation or from screen :-) As the DRAM clock speeds on A31 hardware seem to be really very low, I would suspect that almost any ZQ value would be probably good enough in practice. For A10/A13/A20 hardware we actually have easy tools to measure DRAM reliability. These tools can help to pick good ZQ settings. Something similar may be potentially implemented for A31 too.
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 10a6241..30439dc 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -17,9 +17,7 @@ #include <asm/arch/dram.h> #include <asm/arch/prcm.h> -/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */ -#define DRAM_CLK_DEFAULT 312000000 -#define DRAM_ZQ_DEFAULT 0x78 +#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) struct dram_sun6i_para { u8 bus_width; @@ -48,7 +46,7 @@ static void mctl_sys_init(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int dram_clk_div = 2; - clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div); + clock_set_pll5(DRAM_CLK * dram_clk_div); clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | @@ -173,7 +171,7 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) await_completion(&mctl_phy->pgsr, 0x03, 0x03); - writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1); + writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); writel(MCTL_PIR_STEP1, &mctl_phy->pir); @@ -219,9 +217,9 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) await_completion(&mctl_ctl->sstat, 0x07, 0x01); /* Set number of clks per micro-second */ - writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u); + writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); /* Set number of clks per 100 nano-seconds */ - writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n); + writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); /* Set memory timing registers */ writel(MCTL_TREFI, &mctl_ctl->trefi); writel(MCTL_TMRD, &mctl_ctl->tmrd); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 246cd9a..6162227 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -32,6 +32,23 @@ config MACH_SUN8I endchoice +if MACH_SUN6I + +config DRAM_CLK + int "sun6i dram clock speed" + default 312 + ---help--- + Set the dram clock speed, valid range 240 - 480, must be a multiple + of 24. + +config DRAM_ZQ + int "sun6i dram zq value" + default 123 + ---help--- + Set the dram zq value. + +endif + config SYS_CONFIG_NAME string default "sun4i" if MACH_SUN4I diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index de78a01..9b4968f 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -5,3 +5,5 @@ CONFIG_USB_KEYBOARD=n +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN6I=y +S:CONFIG_TARGET_COLOMBUS=y ++S:CONFIG_DRAM_CLK=288 ++S:CONFIG_DRAM_ZQ=379 diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 40eabce..740b931 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -5,6 +5,8 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb" +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN6I=y +S:CONFIG_TARGET_MELE_M9=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=120 # Ethernet phy power +S:CONFIG_AXP221_DLDO1_VOLT=3300 # USB hub power
It turns out that there is a too large spread between boards to handle this with a default value, turn this into Kconfig options, and set the values the factory images are using for the Colombus and Mele_M9 boards. Note this changes the ZQ default when not overriden through defconfig from 120 to 123, as that is what most boards seem to actually use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 12 +++++------- board/sunxi/Kconfig | 17 +++++++++++++++++ configs/Colombus_defconfig | 2 ++ configs/Mele_M9_defconfig | 2 ++ 4 files changed, 26 insertions(+), 7 deletions(-)