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[U-Boot,v2,7/9] sun6i: Poke magic sram controller register to avoid cache issues

Message ID 1415201888-6194-8-git-send-email-hdegoede@redhat.com
State Superseded
Delegated to: Ian Campbell
Headers show

Commit Message

Hans de Goede Nov. 5, 2014, 3:38 p.m. UTC 
Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/board.c | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6c812fc..9b3e80c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,6 +114,11 @@  void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+	/* Magic (undocmented) value taken from boot0, without this DRAM
+	 * access gets messed up (seems cache related) */
+	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
 		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */