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[U-Boot,21/23] ARM: tegra: Add GIC for Tegra124

Message ID 1408346196-30419-22-git-send-email-thierry.reding@gmail.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Thierry Reding Aug. 18, 2014, 7:16 a.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/dts/tegra124.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Stephen Warren Aug. 20, 2014, 6:45 p.m. UTC | #1 
On 08/18/2014 01:16 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
> complex of Tegra124. U-Boot doesn't use this but subsequent patches will
> add device tree nodes that reference it by phandle.

Matches the kernel, so,
Acked-by: Stephen Warren <swarren@nvidia.com>
diff mbox

Patch

diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index d48f1a34ec3c..510fa332ef98 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -6,6 +6,19 @@ 
 
 / {
 	compatible = "nvidia,tegra124";
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller@50041000 {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x50041000 0x1000>,
+		      <0x50042000 0x2000>,
+		      <0x50044000 0x2000>,
+		      <0x50046000 0x2000>;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
 
 	tegra_car: clock@60006000 {
 		compatible = "nvidia,tegra124-car";