diff mbox

[U-Boot] powerpc/p1010rdb-pb: add support for p1010rdb-pb board

Message ID 1376383388-19389-1-git-send-email-Shengzhou.Liu@freescale.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

Shengzhou Liu Aug. 13, 2013, 8:43 a.m. UTC 
Add support for freescale P1010RDB-PB board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
 board/freescale/p1010rdb/law.c      |    2 -
 board/freescale/p1010rdb/p1010rdb.c |  302 ++++++++++++++++++++++++++++++++---
 board/freescale/p1010rdb/tlb.c      |    4 -
 boards.cfg                          |   21 +++
 include/configs/P1010RDB.h          |  111 ++++++++++---
 5 files changed, 383 insertions(+), 57 deletions(-)

Comments

Scott Wood Aug. 14, 2013, 12:35 a.m. UTC | #1 
On Tue, 2013-08-13 at 16:43 +0800, Shengzhou Liu wrote:
> Add support for freescale P1010RDB-PB board.
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
>  board/freescale/p1010rdb/law.c      |    2 -
>  board/freescale/p1010rdb/p1010rdb.c |  302 ++++++++++++++++++++++++++++++++---
>  board/freescale/p1010rdb/tlb.c      |    4 -
>  boards.cfg                          |   21 +++
>  include/configs/P1010RDB.h          |  111 ++++++++++---
>  5 files changed, 383 insertions(+), 57 deletions(-)
> 
> diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
> index 0045127..ed41a05 100644
> --- a/board/freescale/p1010rdb/law.c
> +++ b/board/freescale/p1010rdb/law.c
> @@ -9,11 +9,9 @@
>  #include <asm/mmu.h>
>  
>  struct law_entry law_table[] = {
> -#ifndef CONFIG_SDCARD
>  	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
>  	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
>  	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
> -#endif
>  };

If this is applicable to the current board as well (is that
P1010RDB-PA?), then it isn't related to adding PB support and thus
belongs in a separate patch.
 
> +uint pin_mux;

This is too generic for a global variable.  Does it even need to be
global?

> -#ifndef CONFIG_SDCARD
>  struct cpld_data {
>  	u8 cpld_ver; /* cpld revision */
> +#if defined(CONFIG_P1010RDB)
>  	u8 pcba_ver; /* pcb revision number */
>  	u8 twindie_ddr3;
>  	u8 res1[6];
> @@ -51,18 +69,16 @@ struct cpld_data {
>  	u8 por1; /* POR Options */
>  	u8 por2; /* POR Options */
>  	u8 por3; /* POR Options */
> +#elif defined(CONFIG_P1010RDB_PB)
> +	u8 rom_loc;
> +#endif
>  };

CONFIG_P1010RDB should be defined if CONFIG_P1010RDB_PB is defined.
Define a new CONFIG_P1010RDB_PA (if that's the appropriate name) for
things that are specifically for the older revision.

> +#if defined(CONFIG_P1010RDB) && defined(DEBUG)
>  void cpld_show(void)
>  {
>  	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
>  
> -	printf("CPLD: V%x.%x PCBA: V%x.0\n",
> -		in_8(&cpld_data->cpld_ver) & 0xF0,
> -		in_8(&cpld_data->cpld_ver) & 0x0F,
> -		in_8(&cpld_data->pcba_ver) & 0x0F);

Why are you removing this?  Where is cpld_show() called?
 
> @@ -246,6 +446,16 @@ void fdt_del_sdhc(void *blob)
>  	}
>  }
>  
> +void fdt_del_ifc(void *blob)
> +{
> +	int nodeoff = 0;
> +
> +	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
> +		"fsl,ifc")) >= 0) {
> +		fdt_del_node(blob, nodeoff);
> +	}
> +}

Is this PB-specific?  If no, why is it in this patch?  If not, why isn't
the caller guarded by the PB ifdef?

> +static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
> +					char * const argv[])
> +{
> +	if (argc < 2)
> +		return CMD_RET_USAGE;
> +	if (strcmp(argv[1], "ifc") == 0)
> +		config_board_mux(MUX_TYPE_IFC);
> +	else if (strcmp(argv[1], "sdhc") == 0)
> +		config_board_mux(MUX_TYPE_SDHC);
> +	else
> +		return CMD_RET_USAGE;
> +	return 0;
> +}
> +
> +U_BOOT_CMD(
> +	mux, 2, 0, pin_mux_cmd,
> +	"configure multiplexing pin for IFC/SDHC bus in runtime",
> +	"bus_type (e.g. mux sdhc)"
> +);

Are you sure this is a good idea?  What happens to the drivers using
said hardware at the time?  Granted they should be idle when not running
a command that actively uses them, but still...  Usually we use hwconfig
for this sort of thing.

> @@ -203,25 +207,24 @@ extern unsigned long get_sdram_size(void);
>  #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
>  #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
>  #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
> -
>  #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
>  #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
>  #define CONFIG_SYS_DDR_RCW_1		0x00000000
>  #define CONFIG_SYS_DDR_RCW_2		0x00000000
> -#define CONFIG_SYS_DDR_CONTROL		0x470C0000	/* Type = DDR3  */
> -#define CONFIG_SYS_DDR_CONTROL_2	0x04401010
> +#define CONFIG_SYS_DDR_CONTROL		0xc70c0008	/* Type = DDR3  */
> +#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
>  #define CONFIG_SYS_DDR_TIMING_4		0x00000001
> -#define CONFIG_SYS_DDR_TIMING_5		0x03402400
> +#define CONFIG_SYS_DDR_TIMING_5		0x02401400
>  
> -#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
> -#define CONFIG_SYS_DDR_TIMING_0_800	0x00330004
> -#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6B4644
> +#define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
> +#define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
> +#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
>  #define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
>  #define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
> -#define CONFIG_SYS_DDR_MODE_1_800	0x40461520
> -#define CONFIG_SYS_DDR_MODE_2_800	0x8000c000
> +#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
> +#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
>  #define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
> -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
> +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608

Shouldn't this be ifdeffed by the board revision?
 
> +#if defined(CONFIG_P1010RDB)
> +#define CONFIG_BOOTMODE \
> +	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0; \
> +mw.b ffb00011 0; mw.b ffb00009 0; reset\0 \
> +	boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0; \
> +mw.b ffb00011 0; mw.b ffb00009 1; reset\0 \
> +	boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0; \
> +mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
> +#elif defined(CONFIG_P1010RDB_PB)
> +#define CONFIG_BOOTMODE \
> +	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0; i2c mw 19 1 2; \
> +i2c mw 19 3 e1; reset\0 \
> +	boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0; i2c mw 19 1 12; \
> +i2c mw 19 3 e1; reset\0 \
> +	boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0; i2c mw 19 1 8; \
> +i2c mw 19 3 f7; reset\0 \
> +	boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0; i2c mw 19 1 0; \
> +i2c mw 19 3 f7; reset\0 \
> +	boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0; i2c mw 19 1 4; \
> +i2c mw 19 3 f3; reset\0"
> +#endif

Don't put newlines in strings.  Do it like this:

#define CONFIG_BOOTMODE \
	"bootb_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0; " \
	"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
	...

-Scott
Scott Wood Sept. 4, 2013, 3:56 p.m. UTC | #2 
On Thu, 2013-08-29 at 06:10 -0500, Liu Shengzhou-B36685 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Wednesday, August 14, 2013 8:35 AM
> > To: Liu Shengzhou-B36685
> > Cc: u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH] powerpc/p1010rdb-pb: add support for p1010rdb-pb
> > board
> > 
> > >  struct law_entry law_table[] = {
> > > -#ifndef CONFIG_SDCARD
> > >  	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
> > >  	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
> > >  	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
> > > -#endif  };
> > 
> > If this is applicable to the current board as well (is that P1010RDB-PA?), then
> > it isn't related to adding PB support and thus belongs in a separate patch.
> > 
> As P1010RDB-PA will no longer be supported officially,

Why?  Don't confuse Freescale supporting the board with U-Boot
supporting the board.

> but we still keep previous code for P1010RDB-PA.
> will add some description for P1010RDB-PA in commit message.

I don't see how this answers my question.

> > > +uint pin_mux;
> > This is too generic for a global variable.  Does it even need to be global?
> 
> Will rename to "static uint sd_ifc_mux", need to be global for invoking in several different functions.

If it's static, it's not global.

> > > +#if defined(CONFIG_P1010RDB) && defined(DEBUG)
> > >  void cpld_show(void)
> > >  {
> > >  	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> > >
> > > -	printf("CPLD: V%x.%x PCBA: V%x.0\n",
> > > -		in_8(&cpld_data->cpld_ver) & 0xF0,
> > > -		in_8(&cpld_data->cpld_ver) & 0x0F,
> > > -		in_8(&cpld_data->pcba_ver) & 0x0F);
> > 
> > Why are you removing this?  Where is cpld_show() called?
> >
> previous code for debug, actually no longer needed, will remove cpld_show().

Make such cleanup a separate patch.

> > > @@ -246,6 +446,16 @@ void fdt_del_sdhc(void *blob)
> > >  	}
> > >  }
> > >
> > > +void fdt_del_ifc(void *blob)
> > > +{
> > > +	int nodeoff = 0;
> > > +
> > > +	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
> > > +		"fsl,ifc")) >= 0) {
> > > +		fdt_del_node(blob, nodeoff);
> > > +	}
> > > +}
> > 
> > Is this PB-specific?  If no, why is it in this patch?  If not, why isn't the
> > caller guarded by the PB ifdef?
> > 
> for both PA and PB, this patch also tune for PA(though PA no longer be supported officially).

Why is it in this patch?

> > > +
> > > +U_BOOT_CMD(
> > > +	mux, 2, 0, pin_mux_cmd,
> > > +	"configure multiplexing pin for IFC/SDHC bus in runtime",
> > > +	"bus_type (e.g. mux sdhc)"
> > > +);
> > 
> > Are you sure this is a good idea?  What happens to the drivers using said
> > hardware at the time?  Granted they should be idle when not running a command
> > that actively uses them, but still...  Usually we use hwconfig for this sort of thing.
> 
> The patch supports two ways simultaneously:
> 1) mux command: for temporary use case in runtime for accessing IFC and SDHC without reboot, 
>    this way is very useful in practice and in some test cases. 
> 2) hwconfig: for long-term use case.

This should be a separate patch from basic board support.

> > > -#define CONFIG_SYS_DDR_MODE_2_800	0x8000c000
> > > +#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
> > > +#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
> > >  #define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
> > > -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
> > > +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
> > 
> > Shouldn't this be ifdeffed by the board revision?
> 
> No, this is for both PA and PB. old parameters were not the optimal, 
> will add some description for P1010RDB-PA in commit message.

Separate patch.

-Scott
Scott Wood Sept. 12, 2013, 12:33 a.m. UTC | #3 
On Wed, 2013-09-11 at 00:58 -0500, Liu Shengzhou-B36685 wrote:

> Scott, please review new version http://patchwork.ozlabs.org/patch/273539/
> 
> 
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Wednesday, September 04, 2013 11:57 PM
> > To: Liu Shengzhou-B36685
> > Cc: Wood Scott-B07421; u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH] powerpc/p1010rdb-pb: add support for p1010rdb-pb
> > board
> > 
> > On Thu, 2013-08-29 at 06:10 -0500, Liu Shengzhou-B36685 wrote:
> > > > -----Original Message-----
> > > > From: Wood Scott-B07421
> > > > Sent: Wednesday, August 14, 2013 8:35 AM
> > > > To: Liu Shengzhou-B36685
> > > > Cc: u-boot@lists.denx.de
> > > > Subject: Re: [U-Boot] [PATCH] powerpc/p1010rdb-pb: add support for
> > > > p1010rdb-pb board
> > > >
> > > > >  struct law_entry law_table[] = {
> > > > > -#ifndef CONFIG_SDCARD
> > > > >  	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
> > > > >  	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
> > > > >  	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M,
> > > > > LAW_TRGT_IF_IFC), -#endif  };
> > > >
> > > > If this is applicable to the current board as well (is that
> > > > P1010RDB-PA?), then it isn't related to adding PB support and thus belongs
> > in a separate patch.
> > > >
> > > As P1010RDB-PA will no longer be supported officially,
> > 
> > Why?  Don't confuse Freescale supporting the board with U-Boot supporting the board.
> 
> Ever PMO team said to remove the code/document of old P1010RDB-PA.


I don't know who PMO is, but they don't dictate what a community project
such as U-Boot does.  If there is a good argument to make for dropping
PA (such as talking about how limited the distribution of the boards has
been so far, though I was not under the impression that it was
particularly limited), then make that argument.  Otherwise, we're
keeping PA support and it's irrelevant that some people in Freescale
don't care about it any more (except for York, of course).

> But I prefer to adhere to reserve code support for old board.

Then what's up with statements like, "we will no longer product and
maintain old board, the change can be regarded as for new board"?


> > > but we still keep previous code for P1010RDB-PA.
> > > will add some description for P1010RDB-PA in commit message.
> > 
> > I don't see how this answers my question.
> 
> I meant new version of this patch would be updated with subject and commit description 
> to cover all the changes of both new and old boards instead of separating patch.


No, please keep PB support separate from anything intended to change how
PA works.


> > > > > +uint pin_mux;
> > > > This is too generic for a global variable.  Does it even need to be global?
> > >
> > > Will rename to "static uint sd_ifc_mux", need to be global for invoking in
> > several different functions.
> > 
> > If it's static, it's not global.
> Use 'static' to limits it as global just in the scope of this module.


My point is that the term "global" usually means program-wide rather
than file-scope, especially when talking about namespacing.


> > > > > +#if defined(CONFIG_P1010RDB) && defined(DEBUG)
> > > > >  void cpld_show(void)
> > > > >  {
> > > > >  	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> > > > >
> > > > > -	printf("CPLD: V%x.%x PCBA: V%x.0\n",
> > > > > -		in_8(&cpld_data->cpld_ver) & 0xF0,
> > > > > -		in_8(&cpld_data->cpld_ver) & 0x0F,
> > > > > -		in_8(&cpld_data->pcba_ver) & 0x0F);
> > > >
> > > > Why are you removing this?  Where is cpld_show() called?
> > > >
> > > previous code for debug, actually no longer needed, will remove cpld_show().
> > 
> > Make such cleanup a separate patch.
> 
> new version of this patch has covered all the changes.
> I don't think it's really necessary as a separate patch. 


I disagree and will not review it in this state (the point is to make it
easier to review -- both now and during future code archaeology).  If
York is happy with it like this, then that's between the two of you...

 

> > > > > +U_BOOT_CMD(
> > > > > +	mux, 2, 0, pin_mux_cmd,
> > > > > +	"configure multiplexing pin for IFC/SDHC bus in runtime",
> > > > > +	"bus_type (e.g. mux sdhc)"
> > > > > +);
> > > >
> > > > Are you sure this is a good idea?  What happens to the drivers using
> > > > said hardware at the time?  Granted they should be idle when not
> > > > running a command that actively uses them, but still...  Usually we use
> > hwconfig for this sort of thing.
> > >
> > > The patch supports two ways simultaneously:
> > > 1) mux command: for temporary use case in runtime for accessing IFC and SDHC
> > without reboot,
> > >    this way is very useful in practice and in some test cases.
> > > 2) hwconfig: for long-term use case.
> > 
> > This should be a separate patch from basic board support.
> Yes, better as a separate patch, but it's not really necessary to split it, we will no longer 
> product and maintain old board, the change can be regarded as for new board.


Huh?  I don't see what this has to do with PA versus PB at all.  It's
not even really about p1010rdb at all.  It's a new feature for
controlling p1010 pin muxing.

-Scott
Scott Wood Sept. 12, 2013, 12:37 a.m. UTC | #4 
On Wed, 2013-09-11 at 19:33 -0500, Scott Wood wrote:
> On Wed, 2013-09-11 at 00:58 -0500, Liu Shengzhou-B36685 wrote: 
> > Scott, please review new version http://patchwork.ozlabs.org/patch/273539/
> > 
> > 
> > > -----Original Message-----
> > > From: Wood Scott-B07421
> > > Sent: Wednesday, September 04, 2013 11:57 PM
> > > To: Liu Shengzhou-B36685
> > > Cc: Wood Scott-B07421; u-boot@lists.denx.de
> > > Subject: Re: [U-Boot] [PATCH] powerpc/p1010rdb-pb: add support for p1010rdb-pb
> > > board

Sorry about the HTML -- the mouse pointer was in the wrong place when
scrolling, and it toggled the option instead of scrolling the
message. :-P

-Scott
diff mbox

Patch

diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index 0045127..ed41a05 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c
@@ -9,11 +9,9 @@ 
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SDCARD
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 06aa800..ef7502f 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -21,10 +21,8 @@ 
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_ifc.h>
 #include <asm/fsl_pci.h>
-
-#ifndef CONFIG_SDCARD
 #include <hwconfig.h>
-#endif
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,10 +31,30 @@  DECLARE_GLOBAL_DATA_PTR;
 #define MUX_CPLD_TDM			0x01
 #define MUX_CPLD_SPICS0_FLASH		0x00
 #define MUX_CPLD_SPICS0_SLIC		0x02
+#define PMUXCR1_IFC_MASK	0x00ffff00
+#define PMUXCR1_SDHC_MASK       0x00fff000
+#define PMUXCR1_SDHC_ENABLE     0x00555000
+
+enum {
+	MUX_TYPE_IFC,
+	MUX_TYPE_SDHC,
+	MUX_TYPE_SPIFLASH,
+	MUX_TYPE_TDM,
+	MUX_TYPE_CAN,
+	MUX_TYPE_CS0_NOR,
+	MUX_TYPE_CS0_NAND,
+};
+
+enum {
+	I2C_READ_BANK,
+	I2C_READ_PCB_VER,
+};
+
+uint pin_mux;
 
-#ifndef CONFIG_SDCARD
 struct cpld_data {
 	u8 cpld_ver; /* cpld revision */
+#if defined(CONFIG_P1010RDB)
 	u8 pcba_ver; /* pcb revision number */
 	u8 twindie_ddr3;
 	u8 res1[6];
@@ -51,18 +69,16 @@  struct cpld_data {
 	u8 por1; /* POR Options */
 	u8 por2; /* POR Options */
 	u8 por3; /* POR Options */
+#elif defined(CONFIG_P1010RDB_PB)
+	u8 rom_loc;
+#endif
 };
 
+#if defined(CONFIG_P1010RDB) && defined(DEBUG)
 void cpld_show(void)
 {
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 
-	printf("CPLD: V%x.%x PCBA: V%x.0\n",
-		in_8(&cpld_data->cpld_ver) & 0xF0,
-		in_8(&cpld_data->cpld_ver) & 0x0F,
-		in_8(&cpld_data->pcba_ver) & 0x0F);
-
-#ifdef CONFIG_DEBUG
 	printf("twindie_ddr =%x\n",
 		in_8(&cpld_data->twindie_ddr3));
 	printf("bank_sel =%x\n",
@@ -85,19 +101,16 @@  void cpld_show(void)
 		in_8(&cpld_data->bcsr2));
 	printf("bcsr3 =%x\n",
 		in_8(&cpld_data->bcsr3));
-#endif
 }
 #endif
 
 int board_early_init_f(void)
 {
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#ifndef CONFIG_SDCARD
 	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
 
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-#endif
 	/*
 	* Reset PCIe slots via GPIO4
 	*/
@@ -109,7 +122,6 @@  int board_early_init_f(void)
 
 int board_early_init_r(void)
 {
-#ifndef CONFIG_SDCARD
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 
@@ -133,7 +145,7 @@  int board_early_init_r(void)
 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
-#endif
+
 	return 0;
 }
 
@@ -144,13 +156,201 @@  void pci_init_board(void)
 }
 #endif /* ifdef CONFIG_PCI */
 
+int config_board_mux(int ctrl_type)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 tmp;
+
+#if defined(CONFIG_P1010RDB)
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x01;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		pin_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		debug("pin mux is configured for IFC, SDHC disabled\n");
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x05;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		pin_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		debug("pin mux is configured for SDHC, IFC disabled\n");
+		break;
+	case MUX_TYPE_SPIFLASH:
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		break;
+	case MUX_TYPE_TDM:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		break;
+	case MUX_TYPE_CAN:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		break;
+	default:
+		break;
+	}
+#elif defined(CONFIG_P1010RDB_PB)
+	uint orig_bus = i2c_get_bus_num();
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		pin_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		pin_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_TDM:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CAN:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NOR:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NAND:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	default:
+		break;
+	}
+	i2c_set_bus_num(orig_bus);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_P1010RDB_PB
+int i2c_pca9557_read(int type)
+{
+	u8 val;
+
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+
+	switch (type) {
+	case I2C_READ_BANK:
+		val = (val & 0x10) >> 4;
+		break;
+	case I2C_READ_PCB_VER:
+		val = ((val & 0x60) >> 5) + 1;
+		break;
+	default:
+		break;
+	}
+
+	return val;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	u8 val;
 
 	cpu = gd->arch.cpu;
-	printf("Board: %sRDB\n", cpu->name);
+#if defined(CONFIG_P1010RDB)
+	printf("Board: %sRDB, ", cpu->name);
+#elif defined(CONFIG_P1010RDB_PB)
+	printf("Board: %sRDB-PB, ", cpu->name);
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+	val = 0x0;  /* no polarity inversion */
+	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
+#endif
+
+#ifdef CONFIG_SDCARD
+	/* switch to IFC to read info from CPLD */
+	config_board_mux(MUX_TYPE_IFC);
+#endif
 
+#if defined(CONFIG_P1010RDB)
+	val = (in_8(&cpld_data->pcba_ver) & 0xF);
+	printf("PCB: v%x.0\n", val);
+#elif defined(CONFIG_P1010RDB_PB)
+	val = in_8(&cpld_data->cpld_ver);
+	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
+	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
+	val = in_8(&cpld_data->rom_loc) & 0xf;
+	puts("Boot from: ");
+	switch (val) {
+	case 0xf:
+		config_board_mux(MUX_TYPE_CS0_NOR);
+		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
+		break;
+	case 0xe:
+		puts("SDHC\n");
+		val = 0x60; /* set pca9557 pin input/output */
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+		break;
+	case 0x5:
+		config_board_mux(MUX_TYPE_IFC);
+		config_board_mux(MUX_TYPE_CS0_NAND);
+		puts("NAND\n");
+		break;
+	case 0x6:
+		config_board_mux(MUX_TYPE_IFC);
+		puts("SPI\n");
+		break;
+	default:
+		puts("unknown\n");
+		break;
+	}
+#endif
 	return 0;
 }
 
@@ -246,6 +446,16 @@  void fdt_del_sdhc(void *blob)
 	}
 }
 
+void fdt_del_ifc(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+		"fsl,ifc")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
 void fdt_disable_uart1(void *blob)
 {
 	int nodeoff;
@@ -289,9 +499,13 @@  void ft_board_setup(void *blob, bd_t *bd)
 		fdt_del_flexcan(blob);
 		fdt_del_node_and_alias(blob, "ethernet2");
 	}
-#ifndef CONFIG_SDCARD
-	/* disable sdhc due to sdhc bug */
-	fdt_del_sdhc(blob);
+
+	/* Delete IFC node as IFC pins are multiplexing with SDHC */
+	if (pin_mux != MUX_TYPE_IFC)
+		fdt_del_ifc(blob);
+	else
+		fdt_del_sdhc(blob);
+
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 		fdt_del_tdm(blob);
 		fdt_del_spi_slic(blob);
@@ -309,14 +523,26 @@  void ft_board_setup(void *blob, bd_t *bd)
 		fdt_del_flexcan(blob);
 		fdt_disable_uart1(blob);
 	}
-#endif
 }
 #endif
 
 #ifndef CONFIG_SDCARD
+void board_reset(void)
+{
+	/* mux to IFC to enable CPLD for reset */
+	if (pin_mux != MUX_TYPE_IFC)
+		config_board_mux(MUX_TYPE_IFC);
+}
+#else
+int board_mmc_init(bd_t *bis)
+{
+	config_board_mux(MUX_TYPE_SDHC);
+	return -1;
+}
+#endif
+
 int misc_init_r(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
@@ -324,7 +550,7 @@  int misc_init_r(void)
 				MPC85xx_PMUXCR_CAN1_UART |
 				MPC85xx_PMUXCR_CAN2_TDM |
 				MPC85xx_PMUXCR_CAN2_UART);
-		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		config_board_mux(MUX_TYPE_CAN);
 	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 				MPC85xx_PMUXCR_CAN1_UART);
@@ -332,13 +558,37 @@  int misc_init_r(void)
 				MPC85xx_PMUXCR_CAN1_TDM);
 		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
-		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
-		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		config_board_mux(MUX_TYPE_TDM);
 	} else {
 		/* defaultly spi_cs_sel to flash */
-		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		config_board_mux(MUX_TYPE_SPIFLASH);
 	}
 
+	if (hwconfig("esdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+
+#ifdef CONFIG_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
 	return 0;
 }
-#endif
+
+static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+					char * const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "ifc") == 0)
+		config_board_mux(MUX_TYPE_IFC);
+	else if (strcmp(argv[1], "sdhc") == 0)
+		config_board_mux(MUX_TYPE_SDHC);
+	else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+U_BOOT_CMD(
+	mux, 2, 0, pin_mux_cmd,
+	"configure multiplexing pin for IFC/SDHC bus in runtime",
+	"bus_type (e.g. mux sdhc)"
+);
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 77a8043..a7af0f6 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -42,7 +42,6 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_SDCARD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_16M, 1),
@@ -51,7 +50,6 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 3, BOOKE_PAGESZ_16M, 1),
-#endif
 
 #ifdef CONFIG_PCI
 	/* *I*G* - PCI */
@@ -66,7 +64,6 @@  struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 #endif
 
-#ifndef CONFIG_SDCARD
 	/* *I*G - Board CPLD  */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -75,7 +72,6 @@  struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
diff --git a/boards.cfg b/boards.cfg
index 944ed4c..5bb6548 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -789,6 +789,27 @@  P1010RDB_NOR_SECBOOT         powerpc     mpc85xx     p1010rdb            freesca
 P1010RDB_SDCARD              powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,SDCARD
 P1010RDB_SPIFLASH            powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,SPIFLASH
 P1010RDB_SPIFLASH_SECBOOT    powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT
+P1010RDB-PB_36BIT_NAND       powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,36BIT,NAND
+P1010RDB-PB_36BIT_NAND_SECBOOT powerpc   mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT
+P1010RDB-PB_36BIT_NOR        powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+36BIT
+P1010RDB-PB_36BIT_NOR_SECBOOT powerpc    mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+36BIT,SECURE_BOOT
+P1010RDB-PB_36BIT_SDCARD     powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+36BIT,SDCARD
+P1010RDB-PB_36BIT_SPIFLASH   powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+36BIT,SPIFLASH
+P1010RDB-PB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx   p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+36BIT,SPIFLASH,SECURE_BOOT
+P1010RDB-PB_NAND             powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+NAND
+P1010RDB-PB_NAND_SECBOOT     powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT
+P1010RDB-PB_NOR              powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB
+P1010RDB-PB_NOR_SECBOOT      powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,SECURE_BOOT
+P1010RDB-PB_SDCARD           powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,SDCARD
+P1010RDB-PB_SPIFLASH         powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,
+SPIFLASH
+P1010RDB-PB_SPIFLASH_SECBOOT powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT
 P1011RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB
 P1011RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,36BIT
 P1011RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,36BIT,SDCARD
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index ba3f7c2..f2493c5 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -120,7 +120,11 @@ 
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#if defined(CONFIG_P1010RDB)
 #define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
+#endif
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
@@ -203,25 +207,24 @@  extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
-
 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0x470C0000	/* Type = DDR3  */
-#define CONFIG_SYS_DDR_CONTROL_2	0x04401010
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0008	/* Type = DDR3  */
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
 #define CONFIG_SYS_DDR_TIMING_4		0x00000001
-#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
 
-#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800	0x00330004
-#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6B4644
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
 #define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
 #define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800	0x40461520
-#define CONFIG_SYS_DDR_MODE_2_800	0x8000c000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 
 /* settings for DDR3 at 667MT/s */
 #define CONFIG_SYS_DDR_TIMING_3_667		0x00010000
@@ -256,10 +259,6 @@  extern unsigned long get_sdram_size(void);
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 
-/* In case of SD card boot, IFC interface is not available because of muxing */
-#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_NO_FLASH
-#else
 /*
  * IFC Definitions
  */
@@ -322,6 +321,8 @@  extern unsigned long get_sdram_size(void);
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#if defined(CONFIG_P1010RDB)
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
@@ -329,13 +330,25 @@  extern unsigned long get_sdram_size(void);
 				| CSOR_NAND_PGS_512	/* Page Size = 512b */ \
 				| CSOR_NAND_SPRZ_16	/* Spare size = 16 */ \
 				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+#endif
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
 
+#if defined(CONFIG_P1010RDB)
 /* NAND Flash Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
 					FTIM0_NAND_TWP(0x0C)   | \
@@ -349,6 +362,22 @@  extern unsigned long get_sdram_size(void);
 					FTIM2_NAND_TREH(0x05) | \
 					FTIM2_NAND_TWHRE(0x0f)
 #define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+#elif defined(CONFIG_P1010RDB_PB)
+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x07)| \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x32)| \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a)  | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3	0x0
+#endif
 
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
@@ -410,7 +439,6 @@  extern unsigned long get_sdram_size(void);
 					FTIM2_GPCM_TCH(0x0) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
-#endif	/* CONFIG_SDCARD */
 
 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
@@ -482,9 +510,20 @@  extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define I2C_PCA9557_ADDR1		0x18
+#define I2C_PCA9557_ADDR2		0x19
+#define I2C_PCA9557_BUS_NUM		0
 
 /* I2C EEPROM */
-#undef CONFIG_ID_EEPROM
+#if defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#endif
 /* enable read and write access to EEPROM */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -567,12 +606,7 @@  extern unsigned long get_sdram_size(void);
 #define CONFIG_LBA48
 #endif /* #ifdef CONFIG_FSL_SATA  */
 
-/*  SD interface will only be available in case of SD boot */
-#ifdef CONFIG_SDCARD
 #define CONFIG_MMC
-#define CONFIG_DEF_HWCONFIG		esdhc
-#endif
-
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
@@ -613,9 +647,14 @@  extern unsigned long get_sdram_size(void);
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
+#if defined(CONFIG_P1010RDB)
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_RANGE	(32 * CONFIG_ENV_SIZE) /* new block size 512K */
+#endif
 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
@@ -708,7 +747,6 @@  extern unsigned long get_sdram_size(void);
 #define CONFIG_HAS_ETH2
 #endif
 
-#define CONFIG_HOSTNAME		P1010RDB
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
@@ -747,7 +785,30 @@  extern unsigned long get_sdram_size(void);
 	"ext2load usb 0:4 $loadaddr $bootfile;"		\
 	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
 	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	CONFIG_BOOTMODE
+
+#if defined(CONFIG_P1010RDB)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0; \
+mw.b ffb00011 0; mw.b ffb00009 0; reset\0 \
+	boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0; \
+mw.b ffb00011 0; mw.b ffb00009 1; reset\0 \
+	boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0; \
+mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0; i2c mw 19 1 2; \
+i2c mw 19 3 e1; reset\0 \
+	boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0; i2c mw 19 1 12; \
+i2c mw 19 3 e1; reset\0 \
+	boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0; i2c mw 19 1 8; \
+i2c mw 19 3 f7; reset\0 \
+	boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0; i2c mw 19 1 0; \
+i2c mw 19 3 f7; reset\0 \
+	boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0; i2c mw 19 1 4; \
+i2c mw 19 3 f3; reset\0"
+#endif
 
 #define CONFIG_RAMBOOTCOMMAND		\
 	"setenv bootargs root=/dev/ram rw "	\