diff mbox

[U-Boot,1/7] ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register

Message ID 1359611525-19017-2-git-send-email-r.sricharan@ti.com
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

SRICHARAN R Jan. 31, 2013, 5:51 a.m. UTC 
From: Lokesh Vutla <lokeshvutla@ti.com>

Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c |   10 +++++++++-
 arch/arm/cpu/armv7/omap-common/emif-common.c   |   21 +++++++++++++++++----
 arch/arm/cpu/armv7/omap5/hwinit.c              |    2 +-
 arch/arm/include/asm/emif.h                    |    6 ++++++
 4 files changed, 33 insertions(+), 6 deletions(-)

Comments

Tom Rini Jan. 31, 2013, 4:29 p.m. UTC | #1 
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On 01/31/2013 12:51 AM, R Sricharan wrote:
> From: Lokesh Vutla <lokeshvutla@ti.com>
> 
> Now SDRAM initialization is done on the basis of omap revision. 
> Instead this should be done on basis of SDRAM type read from 
> EMIF_SDRAM_CONFIG register. This will be helpful to avoid 
> unnessecary cpu checks for new boards
> 
> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: 
> Lokesh Vutla <lokeshvutla@ti.com>

Does this mean the ROM is already doing some basic EMIF programming
here?  I swear I looked down this path before, when I wanted to share
this code with am33xx and the problem is that while the registers
aren't reset on warm boot, on cold boot they always come up in a
default value, for both DDR2 and DDR3.

Or are you able to get by as the platforms come up with different
default values?

- -- 
Tom
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SRICHARAN R Feb. 1, 2013, 6:30 a.m. UTC | #2 
On Thursday 31 January 2013 09:59 PM, Tom Rini wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> On 01/31/2013 12:51 AM, R Sricharan wrote:
>> From: Lokesh Vutla <lokeshvutla@ti.com>
>>
>> Now SDRAM initialization is done on the basis of omap revision.
>> Instead this should be done on basis of SDRAM type read from
>> EMIF_SDRAM_CONFIG register. This will be helpful to avoid
>> unnessecary cpu checks for new boards
>>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by:
>> Lokesh Vutla <lokeshvutla@ti.com>
>
> Does this mean the ROM is already doing some basic EMIF programming
> here?  I swear I looked down this path before, when I wanted to share
> this code with am33xx and the problem is that while the registers
> aren't reset on warm boot, on cold boot they always come up in a
> default value, for both DDR2 and DDR3.
>
> Or are you able to get by as the platforms come up with different
> default values?
>
  Not the ROMCODE, the default value for SDRAM_CONFIG register is
  exported from control module register based on efuse settings. We did
  see that this default value was correct depending upon LPDDR2 or DDR3
  in the case of OMAP.

  So does this mean that am3xx did not have the logic to
  load this register dynamically based on efuse settings ?
  If that is the only exception, then we can hardcode the register
  during startup only in that case. Except for this, where you able
  to use the emif-common driver in your case ?

Regards,
  Sricharan
Tom Rini Feb. 1, 2013, 2:37 p.m. UTC | #3 
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Hash: SHA1

On 02/01/2013 01:30 AM, R Sricharan wrote:
> On Thursday 31 January 2013 09:59 PM, Tom Rini wrote:
>> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
>> 
>> On 01/31/2013 12:51 AM, R Sricharan wrote:
>>> From: Lokesh Vutla <lokeshvutla@ti.com>
>>> 
>>> Now SDRAM initialization is done on the basis of omap
>>> revision. Instead this should be done on basis of SDRAM type
>>> read from EMIF_SDRAM_CONFIG register. This will be helpful to
>>> avoid unnessecary cpu checks for new boards
>>> 
>>> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: 
>>> Lokesh Vutla <lokeshvutla@ti.com>
>> 
>> Does this mean the ROM is already doing some basic EMIF 
>> programming here?  I swear I looked down this path before, when I
>> wanted to share this code with am33xx and the problem is that 
>> while the registers aren't reset on warm boot, on cold boot they
>>  always come up in a default value, for both DDR2 and DDR3.
>> 
>> Or are you able to get by as the platforms come up with
>> different default values?
>> 
> Not the ROMCODE, the default value for SDRAM_CONFIG register is 
> exported from control module register based on efuse settings. We 
> did see that this default value was correct depending upon LPDDR2 
> or DDR3 in the case of OMAP.

OK, good.

> So does this mean that am3xx did not have the logic to load this 
> register dynamically based on efuse settings ? If that is the only
>  exception, then we can hardcode the register during startup only 
> in that case. Except for this, where you able to use the 
> emif-common driver in your case ?

In my initial testing, it was not being setup correctly.  I think it
was between that, and trying to abstract out further the PM-related
changes there wasn't much common EMIF code left, so I set the project
aside at the time.  I'll try and take another whack at it as I know
someone is adding ti814x support currently and did find a good
match-up with this EMIF code rather than the am33xx version, so maybe
that will help me to see what's going on.

And with all of that:
Reviewed-by: Tom Rini <trini@ti.com>

- -- 
Tom
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diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index b1fd277..0b818b8 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -36,6 +36,7 @@ 
 #include <asm/arch/sys_proto.h>
 #include <asm/utils.h>
 #include <asm/omap_gpio.h>
+#include <asm/emif.h>
 
 #ifndef CONFIG_SPL_BUILD
 /*
@@ -299,7 +300,7 @@  static void setup_dplls(void)
 	 * Core DPLL will be locked after setting up EMIF
 	 * using the FREQ_UPDATE method(freq_update_core())
 	 */
-	if (omap_revision() != OMAP5432_ES1_0)
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 		do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
 							DPLL_NO_LOCK, "core");
 	else
@@ -414,6 +415,13 @@  void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
 	if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
 				vcore_reg, offset_code))
 		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
+		/* Configure LDO SRAM "magic" bits */
+		writel(2, (*prcm)->prm_sldo_core_setup);
+		writel(2, (*prcm)->prm_sldo_mpu_setup);
+		writel(2, (*prcm)->prm_sldo_mm_setup);
+	}
 }
 
 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 88253cf..8864abc 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -66,6 +66,19 @@  inline u32 emif_num(u32 base)
 		return 0;
 }
 
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+u32 emif_sdram_type()
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+	return (readl(&emif->emif_sdram_config) &
+		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
 
 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 {
@@ -1079,7 +1092,7 @@  static void do_sdram_init(u32 base)
 	 * OPP to another)
 	 */
 	if (!(in_sdram || warm_reset())) {
-		if (omap_revision() != OMAP5432_ES1_0)
+		if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 			lpddr2_init(base, regs);
 		else
 			ddr3_init(base, regs);
@@ -1264,7 +1277,7 @@  void dmm_init(u32 base)
 void sdram_init(void)
 {
 	u32 in_sdram, size_prog, size_detect;
-	u32 omap_rev = omap_revision();
+	u32 sdram_type = emif_sdram_type();
 
 	debug(">>sdram_init()\n");
 
@@ -1275,7 +1288,7 @@  void sdram_init(void)
 	debug("in_sdram = %d\n", in_sdram);
 
 	if (!(in_sdram || warm_reset())) {
-		if (omap_rev != OMAP5432_ES1_0)
+		if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
 			bypass_dpll(&prcm->cm_clkmode_dpll_core);
 		else
 			writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
@@ -1298,7 +1311,7 @@  void sdram_init(void)
 	}
 
 	/* for the shadow registers to take effect */
-	if (omap_rev != OMAP5432_ES1_0)
+	if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
 		freq_update_core();
 
 	/* Do some testing after the init */
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d0c3ff7..4def422 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -191,7 +191,7 @@  void do_io_settings(void)
 		       (sc_fast << 17) | (sc_fast << 14);
 	writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 
-	if (omap_revision() <= OMAP5430_ES1_0)
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 		io_settings_lpddr2();
 	else
 		io_settings_ddr3();
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ed251ec..0824a80 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1027,6 +1027,11 @@  extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 #define MR8_IO_WIDTH_SHIFT	0x6
 #define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
 
+/* SDRAM TYPE */
+#define EMIF_SDRAM_TYPE_DDR2	0x2
+#define EMIF_SDRAM_TYPE_DDR3	0x3
+#define EMIF_SDRAM_TYPE_LPDDR2	0x4
+
 struct lpddr2_addressing {
 	u8	num_banks;
 	u8	t_REFI_us_x10;
@@ -1156,4 +1161,5 @@  extern u32 *const emif_sizes;
 #endif
 
 void config_data_eye_leveling_samples(u32 emif_base);
+u32 emif_sdram_type(void);
 #endif