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[U-Boot] MX28: MMC: Avoid DMA DCache race condition

Message ID 1346465890-5008-1-git-send-email-marex@denx.de
State Accepted
Commit 97ed12cedf9cd47ddc4553c3fa9f3e8f92cba8c3
Delegated to: Stefano Babic
Headers show

Commit Message

Marek Vasut Sept. 1, 2012, 2:18 a.m. UTC
This patch prevents dcache-related problem. The problem manifested
itself on the SPI driver, this is just a port to the MMC driver.

The scenario is the same. In case an "mmc read" is issued to a
buffer which was written right before it and data cache is enabled,
the cache eviction might happen during the DMA transfer into the
buffer, therefore corrupting the buffer. Clear any cache lines that
might contain the buffer to prevent such issue.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
---
 drivers/mmc/mxsmmc.c |    4 ++++
 1 file changed, 4 insertions(+)

Comments

Stefano Babic Sept. 6, 2012, 12:20 p.m. UTC | #1
On 01/09/2012 04:18, Marek Vasut wrote:
> This patch prevents dcache-related problem. The problem manifested
> itself on the SPI driver, this is just a port to the MMC driver.
> 
> The scenario is the same. In case an "mmc read" is issued to a
> buffer which was written right before it and data cache is enabled,
> the cache eviction might happen during the DMA transfer into the
> buffer, therefore corrupting the buffer. Clear any cache lines that
> might contain the buffer to prevent such issue.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Otavio Salvador <otavio@ossystems.com.br>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 9a98c6b..c80b41b 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -119,6 +119,10 @@  static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
 			(uint32_t)(priv->desc->cmd.address + cache_data_count));
 	}
 
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
+			(uint32_t)(priv->desc->cmd.address + cache_data_count));
+
 	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 				(data_count << MXS_DMA_DESC_BYTES_OFFSET);