| Message ID | 1344881442-22671-6-git-send-email-msm@freescale.com |
|---|---|
| State | Accepted, archived |
| Delegated to: | Andy Fleming |
| Headers | show |
On 08/13/2012 01:10 PM, Matthew McClintock wrote: > This change reduces the SPL size by removing the redundant syncs produced > by out_be32 and just replies on one final sync > > Done with: > > sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` > > Signed-off-by: Matthew McClintock <msm@freescale.com> > --- > nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- > nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- > nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- > 3 files changed, 71 insertions(+), 73 deletions(-) This should come first if the other patches break without it, to preserve bisectability. Note that I'm going to try to convert this stuff (at least one board as an example, but hopefully it should be easy enough to do additional boards once the first is done) to the new spl Really Soon Now(tm), so it doesn't make much sense to fiddle around with the old stuff right now unless I miss the merge window. I'll incorporate these changes into the new-spl version. I may do that by applying these patches first, but I'd rather they not go via the mpc85xx tree (and please CC me on NAND patches). -Scott
On Mon, Aug 13, 2012 at 6:23 PM, Scott Wood <scottwood@freescale.com> wrote: > On 08/13/2012 01:10 PM, Matthew McClintock wrote: >> This change reduces the SPL size by removing the redundant syncs produced >> by out_be32 and just replies on one final sync >> >> Done with: >> >> sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` >> >> Signed-off-by: Matthew McClintock <msm@freescale.com> >> --- >> nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- >> nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- >> nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- >> 3 files changed, 71 insertions(+), 73 deletions(-) > > This should come first if the other patches break without it, to > preserve bisectability. I think they all work on at least some compilers.... not that that's extremely helpful. -M > > Note that I'm going to try to convert this stuff (at least one board as > an example, but hopefully it should be easy enough to do additional > boards once the first is done) to the new spl Really Soon Now(tm), so it > doesn't make much sense to fiddle around with the old stuff right now > unless I miss the merge window. I'll incorporate these changes into the > new-spl version. I may do that by applying these patches first, but I'd > rather they not go via the mpc85xx tree (and please CC me on NAND patches). > > -Scott > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
On 08/13/2012 06:31 PM, McClintock Matthew-B29882 wrote: > On Mon, Aug 13, 2012 at 6:23 PM, Scott Wood <scottwood@freescale.com> wrote: >> On 08/13/2012 01:10 PM, Matthew McClintock wrote: >>> This change reduces the SPL size by removing the redundant syncs produced >>> by out_be32 and just replies on one final sync >>> >>> Done with: >>> >>> sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` >>> >>> Signed-off-by: Matthew McClintock <msm@freescale.com> >>> --- >>> nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- >>> nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- >>> nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- >>> 3 files changed, 71 insertions(+), 73 deletions(-) >> >> This should come first if the other patches break without it, to >> preserve bisectability. > > I think they all work on at least some compilers.... not that that's > extremely helpful. Was this patch meant to free up room for the other patches, or was it just bundled in because it's touching the same code? -Scott
On Mon, Aug 13, 2012 at 6:34 PM, Scott Wood <scottwood@freescale.com> wrote: > On 08/13/2012 06:31 PM, McClintock Matthew-B29882 wrote: >> On Mon, Aug 13, 2012 at 6:23 PM, Scott Wood <scottwood@freescale.com> wrote: >>> On 08/13/2012 01:10 PM, Matthew McClintock wrote: >>>> This change reduces the SPL size by removing the redundant syncs produced >>>> by out_be32 and just replies on one final sync >>>> >>>> Done with: >>>> >>>> sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` >>>> >>>> Signed-off-by: Matthew McClintock <msm@freescale.com> >>>> --- >>>> nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- >>>> nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- >>>> nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- >>>> 3 files changed, 71 insertions(+), 73 deletions(-) >>> >>> This should come first if the other patches break without it, to >>> preserve bisectability. >> >> I think they all work on at least some compilers.... not that that's >> extremely helpful. > > Was this patch meant to free up room for the other patches, or was it > just bundled in because it's touching the same code? I believe I was tasked with fixing builds on our newer toolchains (or was it older toolchains?) since some combinations ran out of space. The exact reasoning escapes me, also why did it last a well... I can reorder them if you would like... -M
On 08/13/2012 06:23 PM, Scott Wood wrote: > On 08/13/2012 01:10 PM, Matthew McClintock wrote: >> This change reduces the SPL size by removing the redundant syncs produced >> by out_be32 and just replies on one final sync >> >> Done with: >> >> sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` >> >> Signed-off-by: Matthew McClintock <msm@freescale.com> >> --- >> nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- >> nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- >> nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- >> 3 files changed, 71 insertions(+), 73 deletions(-) > > This should come first if the other patches break without it, to > preserve bisectability. > > Note that I'm going to try to convert this stuff (at least one board as > an example, but hopefully it should be easy enough to do additional > boards once the first is done) to the new spl Really Soon Now(tm), so it > doesn't make much sense to fiddle around with the old stuff right now > unless I miss the merge window. I'll incorporate these changes into the > new-spl version. I may do that by applying these patches first, but I'd > rather they not go via the mpc85xx tree (and please CC me on NAND patches). I'm not going to have this working by the end of the merge window, so these patches can go in as is. Andy, do you want to take them or should I? -Scott
I'm ok if you take them. I should be doing a push today, so either way works for me. On Aug 18, 2012, at 2:05 PM, Scott Wood wrote: > On 08/13/2012 06:23 PM, Scott Wood wrote: >> On 08/13/2012 01:10 PM, Matthew McClintock wrote: >>> This change reduces the SPL size by removing the redundant syncs produced >>> by out_be32 and just replies on one final sync >>> >>> Done with: >>> >>> sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` >>> >>> Signed-off-by: Matthew McClintock <msm@freescale.com> >>> --- >>> nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- >>> nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- >>> nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- >>> 3 files changed, 71 insertions(+), 73 deletions(-) >> >> This should come first if the other patches break without it, to >> preserve bisectability. >> >> Note that I'm going to try to convert this stuff (at least one board as >> an example, but hopefully it should be easy enough to do additional >> boards once the first is done) to the new spl Really Soon Now(tm), so it >> doesn't make much sense to fiddle around with the old stuff right now >> unless I miss the merge window. I'll incorporate these changes into the >> new-spl version. I may do that by applying these patches first, but I'd >> rather they not go via the mpc85xx tree (and please CC me on NAND patches). > > I'm not going to have this working by the end of the merge window, so > these patches can go in as is. Andy, do you want to take them or should I? > > -Scott >
On 08/20/2012 11:11 AM, Andy Fleming wrote: > I'm ok if you take them. I should be doing a push today, so either way works for me. If you're doing one today, go ahead and take them: Acked-by: Scott Wood <scottwood@freescale.com> -Scott
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 931e562..7190b00 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -36,39 +36,37 @@ void sdram_init(void) /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); if (ddr_freq_mhz < 700) { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_667); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); } else { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_800); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); } - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); /* P1014 and it's derivatives support max 16bit DDR width */ if (svr == SVR_P1014) { diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 9309936..a63fc8d 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -34,28 +34,28 @@ void sdram_init(void) set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); - out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); + __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); + __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); /* Set, but do not enable the memory */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); asm volatile("sync;isync"); udelay(500); diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c index e7906e8..db9b571 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -33,32 +33,32 @@ void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); #endif - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); /* Set, but do not enable the memory */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); asm volatile("sync;isync"); udelay(500); @@ -91,13 +91,13 @@ void board_init_f(ulong bootflag) #ifndef CONFIG_QE /* init DDR3 reset signal */ - out_be32(&pgpio->gpdir, 0x02000000); - out_be32(&pgpio->gpodr, 0x00200000); - out_be32(&pgpio->gpdat, 0x00000000); + __raw_writel(0x02000000, &pgpio->gpdir); + __raw_writel(0x00200000, &pgpio->gpodr); + __raw_writel(0x00000000, &pgpio->gpdat); udelay(1000); - out_be32(&pgpio->gpdat, 0x00200000); + __raw_writel(0x00200000, &pgpio->gpdat); udelay(1000); - out_be32(&pgpio->gpdir, 0x00000000); + __raw_writel(0x00000000, &pgpio->gpdir); #endif /* Initialize the DDR3 */
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync Done with: sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` Signed-off-by: Matthew McClintock <msm@freescale.com> --- nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)