| Message ID | 1328085078-3104-1-git-send-email-Shengzhou.Liu@freescale.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
> when missing USB PHY clock and issuing "usb start" at u-boot prompt, > writing to or_portsc register will cause CPU halt. We should check > USBGP[PHY_CLK_VALID] bit at the first time in ehci_hcd_init() to avoid CPU > hang in this case. > > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > --- > drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- > 1 files changed, 19 insertions(+), 3 deletions(-) > Hi, what's the status of this patch/patchset? Thanks M
> -----Original Message----- > From: Marek Vasut [mailto:marex@denx.de] > Sent: Monday, February 27, 2012 7:13 AM > To: u-boot@lists.denx.de > Cc: Liu Shengzhou-B36685 > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > missing USB PHY clock > > > when missing USB PHY clock and issuing "usb start" at u-boot prompt, > > writing to or_portsc register will cause CPU halt. We should check > > USBGP[PHY_CLK_VALID] bit at the first time in ehci_hcd_init() to > avoid > > CPU hang in this case. > > > > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > > --- > > drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- > > 1 files changed, 19 insertions(+), 3 deletions(-) > > > Hi, > > what's the status of this patch/patchset? > > Thanks > M Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 platform, which not contains this bit. - P1023/P3041/P5020 etc, have this bit - P3060/4080/PSC913x do have this bit, but not mentioned in RM. - P1022(perhaps and other) has no this bit I'm waiting for the response from FSL silicon team to confirm whether there is other platform not including this bit or not, so this patch maybe have to be pending until I get confirmation. Thanks, Shengzhou
Pinging you on this, again. Also, I've now moved the patch to Marek's queue, instead of mine. On Sun, Feb 26, 2012 at 8:44 PM, Liu Shengzhou-B36685 <B36685@freescale.com> wrote: > >> -----Original Message----- >> From: Marek Vasut [mailto:marex@denx.de] >> Sent: Monday, February 27, 2012 7:13 AM >> To: u-boot@lists.denx.de >> Cc: Liu Shengzhou-B36685 >> Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when >> missing USB PHY clock >> >> > when missing USB PHY clock and issuing "usb start" at u-boot prompt, >> > writing to or_portsc register will cause CPU halt. We should check >> > USBGP[PHY_CLK_VALID] bit at the first time in ehci_hcd_init() to >> avoid >> > CPU hang in this case. >> > >> > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> >> > --- >> > drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- >> > 1 files changed, 19 insertions(+), 3 deletions(-) >> > >> Hi, >> >> what's the status of this patch/patchset? >> >> Thanks >> M > > Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 platform, which not contains this bit. > - P1023/P3041/P5020 etc, have this bit > - P3060/4080/PSC913x do have this bit, but not mentioned in RM. > - P1022(perhaps and other) has no this bit > I'm waiting for the response from FSL silicon team to confirm whether there is other platform > not including this bit or not, so this patch maybe have to be pending until I get confirmation. > > Thanks, > Shengzhou > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
Dear Andy Fleming, > Pinging you on this, again. Also, I've now moved the patch to Marek's > queue, instead of mine. Thanks! Did the FSL silicon team respond already? > > On Sun, Feb 26, 2012 at 8:44 PM, Liu Shengzhou-B36685 > > <B36685@freescale.com> wrote: > >> -----Original Message----- > >> From: Marek Vasut [mailto:marex@denx.de] > >> Sent: Monday, February 27, 2012 7:13 AM > >> To: u-boot@lists.denx.de > >> Cc: Liu Shengzhou-B36685 > >> Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > >> missing USB PHY clock > >> > >> > when missing USB PHY clock and issuing "usb start" at u-boot prompt, > >> > writing to or_portsc register will cause CPU halt. We should check > >> > USBGP[PHY_CLK_VALID] bit at the first time in ehci_hcd_init() to > >> > >> avoid > >> > >> > CPU hang in this case. > >> > > >> > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > >> > --- > >> > drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- > >> > 1 files changed, 19 insertions(+), 3 deletions(-) > >> > >> Hi, > >> > >> what's the status of this patch/patchset? > >> > >> Thanks > >> M > > > > Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 > > platform, which not contains this bit. - P1023/P3041/P5020 etc, have > > this bit > > - P3060/4080/PSC913x do have this bit, but not mentioned in RM. > > - P1022(perhaps and other) has no this bit > > I'm waiting for the response from FSL silicon team to confirm whether > > there is other platform not including this bit or not, so this patch > > maybe have to be pending until I get confirmation. > > > > Thanks, > > Shengzhou > > > > > > _______________________________________________ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot Best regards, Marek Vasut
Hello guys, I didn't get an explicit list from silicon team to point out which platforms contain this PHY_CLK_VALID bit or not, Someone said all platforms have this bit, it's not true, at least we found P4080 and P1022 no this bit. I'll trace it later. This patch is not necessary for boards with USB PHY clock valid, just for those case of USB PHY clock invalid. Thanks, Shengzhou > -----Original Message----- > From: Marek Vasut [mailto:marex@denx.de] > Sent: Thursday, April 19, 2012 6:57 AM > To: Andy Fleming > Cc: Liu Shengzhou-B36685; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when missing > USB PHY clock > > Dear Andy Fleming, > > > Pinging you on this, again. Also, I've now moved the patch to Marek's > > queue, instead of mine. > > Thanks! Did the FSL silicon team respond already? > > > > > On Sun, Feb 26, 2012 at 8:44 PM, Liu Shengzhou-B36685 > > > > <B36685@freescale.com> wrote: > > >> -----Original Message----- > > >> From: Marek Vasut [mailto:marex@denx.de] > > >> Sent: Monday, February 27, 2012 7:13 AM > > >> To: u-boot@lists.denx.de > > >> Cc: Liu Shengzhou-B36685 > > >> Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > > >> missing USB PHY clock > > >> > > >> > when missing USB PHY clock and issuing "usb start" at u-boot > > >> > prompt, writing to or_portsc register will cause CPU halt. We > > >> > should check USBGP[PHY_CLK_VALID] bit at the first time in > > >> > ehci_hcd_init() to > > >> > > >> avoid > > >> > > >> > CPU hang in this case. > > >> > > > >> > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > > >> > --- > > >> > drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- > > >> > 1 files changed, 19 insertions(+), 3 deletions(-) > > >> > > >> Hi, > > >> > > >> what's the status of this patch/patchset? > > >> > > >> Thanks > > >> M > > > > > > Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 > > > platform, which not contains this bit. - P1023/P3041/P5020 etc, have > > > this bit > > > - P3060/4080/PSC913x do have this bit, but not mentioned in RM. > > > - P1022(perhaps and other) has no this bit I'm waiting for the > > > response from FSL silicon team to confirm whether there is other > > > platform not including this bit or not, so this patch maybe have to > > > be pending until I get confirmation. > > > > > > Thanks, > > > Shengzhou > > > > > > > > > _______________________________________________ > > > U-Boot mailing list > > > U-Boot@lists.denx.de > > > http://lists.denx.de/mailman/listinfo/u-boot > > Best regards, > Marek Vasut
Dear Liu Shengzhou-B36685, > Hello guys, > > I didn't get an explicit list from silicon team to point out which > platforms contain this PHY_CLK_VALID bit or not, Someone said all > platforms have this bit, it's not true, at least we found P4080 and P1022 > no this bit. I'll trace it later. > > This patch is not necessary for boards with USB PHY clock valid, just for > those case of USB PHY clock invalid. Roger that, thanks a lot :) > > Thanks, > Shengzhou > > > -----Original Message----- > > From: Marek Vasut [mailto:marex@denx.de] > > Sent: Thursday, April 19, 2012 6:57 AM > > To: Andy Fleming > > Cc: Liu Shengzhou-B36685; u-boot@lists.denx.de > > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > > missing USB PHY clock > > > > Dear Andy Fleming, > > > > > Pinging you on this, again. Also, I've now moved the patch to Marek's > > > queue, instead of mine. > > > > Thanks! Did the FSL silicon team respond already? > > > > > On Sun, Feb 26, 2012 at 8:44 PM, Liu Shengzhou-B36685 > > > > > > <B36685@freescale.com> wrote: > > > >> -----Original Message----- > > > >> From: Marek Vasut [mailto:marex@denx.de] > > > >> Sent: Monday, February 27, 2012 7:13 AM > > > >> To: u-boot@lists.denx.de > > > >> Cc: Liu Shengzhou-B36685 > > > >> Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > > > >> missing USB PHY clock > > > >> > > > >> > when missing USB PHY clock and issuing "usb start" at u-boot > > > >> > prompt, writing to or_portsc register will cause CPU halt. We > > > >> > should check USBGP[PHY_CLK_VALID] bit at the first time in > > > >> > ehci_hcd_init() to > > > >> > > > >> avoid > > > >> > > > >> > CPU hang in this case. > > > >> > > > > >> > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> > > > >> > --- > > > >> > > > > >> > drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- > > > >> > 1 files changed, 19 insertions(+), 3 deletions(-) > > > >> > > > >> Hi, > > > >> > > > >> what's the status of this patch/patchset? > > > >> > > > >> Thanks > > > >> M > > > > > > > > Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 > > > > platform, which not contains this bit. - P1023/P3041/P5020 etc, have > > > > this bit > > > > > > > > - P3060/4080/PSC913x do have this bit, but not mentioned in RM. > > > > - P1022(perhaps and other) has no this bit I'm waiting for the > > > > > > > > response from FSL silicon team to confirm whether there is other > > > > platform not including this bit or not, so this patch maybe have to > > > > be pending until I get confirmation. > > > > > > > > Thanks, > > > > Shengzhou > > > > > > > > > > > > _______________________________________________ > > > > U-Boot mailing list > > > > U-Boot@lists.denx.de > > > > http://lists.denx.de/mailman/listinfo/u-boot > > > > Best regards, > > Marek Vasut Best regards, Marek Vasut
Dear Liu Shengzhou-B36685, > Hello guys, > > I didn't get an explicit list from silicon team to point out which > platforms contain this PHY_CLK_VALID bit or not, Someone said all > platforms have this bit, it's not true, at least we found P4080 and P1022 > no this bit. I'll trace it later. > > This patch is not necessary for boards with USB PHY clock valid, just for > those case of USB PHY clock invalid. > > Thanks, > Shengzhou [...] So did anything new happen here or shall I just discard the patch? Best regards, Marek Vasut
> -----Original Message----- > From: Marek Vasut [mailto:marex@denx.de] > Sent: Tuesday, October 16, 2012 2:23 PM > To: Liu Shengzhou-B36685 > Cc: Andy Fleming; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > missing USB PHY clock > > Dear Liu Shengzhou-B36685, > > > Hello guys, > > > > I didn't get an explicit list from silicon team to point out which > > platforms contain this PHY_CLK_VALID bit or not, Someone said all > > platforms have this bit, it's not true, at least we found P4080 and > > P1022 no this bit. I'll trace it later. > > > > This patch is not necessary for boards with USB PHY clock valid, just > > for those case of USB PHY clock invalid. > > > > Thanks, > > Shengzhou > [...] > > So did anything new happen here or shall I just discard the patch? > > Best regards, > Marek Vasut Hello Marek, I re-submitted a new version as below, please review it. http://patchwork.ozlabs.org/patch/192178/ Thanks, Shengzhou
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index b2d294e..cc29375 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -31,6 +31,18 @@ #include "ehci.h" #include "ehci-core.h" +/* Check USB PHY clock valid */ +static int usb_phy_clk_valid(struct usb_ehci *ehci) +{ + if ((!(in_be32(&ehci->control) & PHY_CLK_VALID)) && + (!in_be32(&ehci->prictrl))) { + printf("WARNING: USB PHY clock invalid\n"); + return 0; + } else { + return 1; + } +} + /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -59,6 +71,9 @@ int ehci_hcd_init(void) out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); + /* Enable interface. */ + setbits_be32(&ehci->control, USB_EN); + /* Init phy */ if (hwconfig_sub("usb1", "phy_type")) phy_type = hwconfig_subarg("usb1", "phy_type", &len); @@ -82,6 +97,8 @@ int ehci_hcd_init(void) setbits_be32(&ehci->control, UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ #endif + if (!usb_phy_clk_valid(ehci)) + return -1; out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); } else { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) @@ -89,12 +106,11 @@ int ehci_hcd_init(void) setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); udelay(1000); /* delay required for PHY Clk to appear */ #endif + if (!usb_phy_clk_valid(ehci)) + return -1; out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); } - /* Enable interface. */ - setbits_be32(&ehci->control, USB_EN); - out_be32(&ehci->prictrl, 0x0000000c); out_be32(&ehci->age_cnt_limit, 0x00000040); out_be32(&ehci->sictrl, 0x00000001);
when missing USB PHY clock and issuing "usb start" at u-boot prompt, writing to or_portsc register will cause CPU halt. We should check USBGP[PHY_CLK_VALID] bit at the first time in ehci_hcd_init() to avoid CPU hang in this case. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> --- drivers/usb/host/ehci-fsl.c | 22 +++++++++++++++++++--- 1 files changed, 19 insertions(+), 3 deletions(-)