[U-Boot,v3,2/2] mpc85xx: support for Freescale COM Express P2020

This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip RAM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---

The CCSR relocation issue is solved by Timur's 5 part patchset containing
the patch "powerpc/85xx: resize the boot page TLB before relocating CCSR".

This patch is checkpatch clean using the checkpatch and configuration file
provided in the patch from Joe Hershberger titled "tools: checkpatch.pl
from Linux added to tools".

Changes v2 -> v3:
- re-enable CCSR relocation

Changes v1 -> v2:
- fix checkpatch warnings
- remove all references to NAND
- update to top of tree U-Boot
- remove CCSR relocation (top of tree code doesn't work)

 MAINTAINERS                           |    4 +
 arch/powerpc/include/asm/immap_85xx.h |    1 +
 board/freescale/p2020come/Makefile    |   46 +++
 board/freescale/p2020come/ddr.c       |  245 ++++++++++++++
 board/freescale/p2020come/law.c       |   36 ++
 board/freescale/p2020come/p2020come.c |  401 +++++++++++++++++++++++
 board/freescale/p2020come/tlb.c       |  100 ++++++
 boards.cfg                            |    2 +
 include/configs/P2020COME.h           |  569 +++++++++++++++++++++++++++++++++
 9 files changed, 1404 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/p2020come/Makefile
 create mode 100644 board/freescale/p2020come/ddr.c
 create mode 100644 board/freescale/p2020come/law.c
 create mode 100644 board/freescale/p2020come/p2020come.c
 create mode 100644 board/freescale/p2020come/tlb.c
 create mode 100644 include/configs/P2020COME.h

On Nov 10, 2011, at 3:11 PM, Ira W. Snyder wrote:

> This adds support for the Freescale COM Express P2020 board. This board
> is similar to the P1_P2_RDB, but has some extra (as well as missing)
> peripherals.
> 
> Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
> Using the HRESET_REQ register does not work.
> 
> This board has no NOR flash, and can only be booted via SD or SPI. This
> procedure is documented in Freescale Document Number AN3659 "Booting
> from On-Chip RAM (eSDHC or eSPI)." Some alternative documentation is
> provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
> Processor Reference Manual" (section 4.5).
> 
> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
> ---
> 


> diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
> new file mode 100644
> index 0000000..dd2a4dd
> --- /dev/null
> +++ b/board/freescale/p2020come/ddr.c
> @@ -0,0 +1,245 @@
> +/*
> + * Copyright 2009, 2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/mmu.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/processor.h>
> +#include <asm/fsl_ddr_sdram.h>
> +#include <asm/io.h>
> +#include <asm/fsl_law.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
> +#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
> +#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
> +#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
> +#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
> +#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
> +#define CONFIG_SYS_DDR_ZQ_CONTROL	0x00000000
> +#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x00000000
> +#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
> +#define CONFIG_SYS_DDR_RCW_1		0x00000000
> +#define CONFIG_SYS_DDR_RCW_2		0x00000000
> +#define CONFIG_SYS_DDR_CONTROL		0x43000000	/* Type = DDR2*/
> +#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
> +#define CONFIG_SYS_DDR_TIMING_4		0x00000000
> +#define CONFIG_SYS_DDR_TIMING_5		0x00000000
> +
> +#define CONFIG_SYS_DDR_TIMING_3_400	0x00010000
> +#define CONFIG_SYS_DDR_TIMING_0_400	0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1_400	0x39355322
> +#define CONFIG_SYS_DDR_TIMING_2_400	0x1f9048ca
> +#define CONFIG_SYS_DDR_CLK_CTRL_400	0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_400	0x00480432
> +#define CONFIG_SYS_DDR_MODE_2_400	0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_400	0x06180100
> +
> +#define CONFIG_SYS_DDR_TIMING_3_533	0x00020000
> +#define CONFIG_SYS_DDR_TIMING_0_533	0x00260802
> +#define CONFIG_SYS_DDR_TIMING_1_533	0x4c47c432
> +#define CONFIG_SYS_DDR_TIMING_2_533	0x0f9848ce
> +#define CONFIG_SYS_DDR_CLK_CTRL_533	0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_533	0x00040642
> +#define CONFIG_SYS_DDR_MODE_2_533	0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_533	0x08200100
> +
> +#define CONFIG_SYS_DDR_TIMING_3_667	0x00030000
> +#define CONFIG_SYS_DDR_TIMING_0_667	0x55770802
> +#define CONFIG_SYS_DDR_TIMING_1_667	0x5f599543
> +#define CONFIG_SYS_DDR_TIMING_2_667	0x0fa074d1
> +#define CONFIG_SYS_DDR_CLK_CTRL_667	0x03000000
> +#define CONFIG_SYS_DDR_MODE_1_667	0x00040852
> +#define CONFIG_SYS_DDR_MODE_2_667	0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_667	0x0a280100
> +
> +#define CONFIG_SYS_DDR_TIMING_3_800	0x00040000
> +#define CONFIG_SYS_DDR_TIMING_0_800	0x00770802
> +#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b6543
> +#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa074d1
> +#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
> +#define CONFIG_SYS_DDR_MODE_1_800	0x00040852
> +#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
> +#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
> +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
> +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
> +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
> +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
> +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
> +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
> +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
> +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
> +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
> +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
> +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
> +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
> +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
> +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
> +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
> +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
> +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
> +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
> +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
> +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
> +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
> +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
> +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
> +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
> +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
> +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
> +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
> +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
> +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
> +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
> +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
> +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
> +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
> +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
> +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
> +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> +};
> +
> +/*
> + * Fixed sdram init -- doesn't use serial presence detect.
> + */
> +
> +phys_size_t fixed_sdram(void)
> +{
> +	char buf[32];
> +	fsl_ddr_cfg_regs_t ddr_cfg_regs;
> +	size_t ddr_size;
> +	struct cpu_type *cpu;
> +	ulong ddr_freq, ddr_freq_mhz;
> +
> +	cpu = gd->cpu;
> +	/* P1020 and it's derivatives support max 32bit DDR width */
> +	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
> +		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
> +		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);

These checks don't make sense if you are a P2020 SoC

> +	} else {
> +		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> +	}
> +#if defined(CONFIG_SYS_RAMBOOT)
> +	return ddr_size;
> +#endif
> +	ddr_freq = get_ddr_freq(0);
> +	ddr_freq_mhz = ddr_freq / 1000000;
> +
> +	printf("Configuring DDR for %s MT/s data rate\n",
> +				strmhz(buf, ddr_freq));
> +
> +	if (ddr_freq_mhz <= 400)
> +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
> +	else if (ddr_freq_mhz <= 533)
> +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
> +	else if (ddr_freq_mhz <= 667)
> +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
> +	else if (ddr_freq_mhz <= 800)
> +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
> +	else
> +		panic("Unsupported DDR data rate %s MT/s data rate\n",
> +					strmhz(buf, ddr_freq));

Does the board really support different DDR freq or is this copy / paste?

> +
> +	/* P1020 and it's derivatives support max 32bit DDR width */
> +	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
> +		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
> +		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
> +		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
> +	}

Same comment as above

> +
> +	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
> +
> +	set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
> +	return ddr_size;
> +}
> diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
> new file mode 100644
> index 0000000..56508db
> --- /dev/null
> +++ b/board/freescale/p2020come/law.c
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/fsl_law.h>
> +#include <asm/mmu.h>
> +
> +struct law_entry law_table[] = {
> +	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> +	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> +	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
> +	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
> +	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
> +	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),

We normally set these up dynamically.

> +};
> +
> +int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
> new file mode 100644
> index 0000000..2e334cf
> --- /dev/null
> +++ b/board/freescale/p2020come/p2020come.c
> @@ -0,0 +1,401 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <hwconfig.h>
> +#include <command.h>
> +#include <asm/processor.h>
> +#include <asm/mmu.h>
> +#include <asm/cache.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/fsl_serdes.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +#include <fsl_mdio.h>
> +#include <tsec.h>
> +#include <vsc7385.h>
> +#include <netdev.h>
> +#include <mmc.h>
> +#include <malloc.h>
> +#include <i2c.h>
> +
> +#if defined(CONFIG_PCI)
> +#include <asm/fsl_pci.h>
> +#include <pci.h>
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_PCI)
> +void pci_init_board(void)
> +{
> +	fsl_pcie_init_board(0);
> +}
> +
> +void ft_pci_board_setup(void *blob)
> +{
> +	FT_FSL_PCI_SETUP;
> +}
> +#endif
> +
> +/*
> + * GPIO
> + * 0 - 3: CarryBoard Input;
> + * 4 - 7: CarryBoard Output;
> + * 8 : Mux as SDHC_CD (card detection)
> + * 9 : Mux as SDHC_WP
> + * 10 : Clear Watchdog timer
> + * 11 : LED Input
> + * 12 : Output to 1
> + * 13 : Open Drain
> + * 14 : LED Output
> + * 15 : Switch Input
> + */
> +#define GPIO_DIR		0x0f3a0000
> +#define GPIO_ODR		0x00000000
> +
> +#define BOARD_PERI_RST_SET	(VSC7385_RST_SET | SLIC_RST_SET | \
> +				 SGMII_PHY_RST_SET | PCIE_RST_SET | \
> +				 RGMII_PHY_RST_SET)
> +
> +#define SYSCLK_MASK	0x00200000
> +#define BOARDREV_MASK	0x10100000
> +#define BOARDREV_B	0x10100000
> +#define BOARDREV_C	0x00100000
> +#define BOARDREV_D	0x00000000
> +
> +#define SYSCLK_66	66666666
> +#define SYSCLK_50	50000000
> +#define SYSCLK_100	100000000
> +
> +unsigned long get_board_sys_clk(ulong dummy)
> +{
> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> +
> +	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> +	switch (ddr_ratio) {
> +	case 0x0C:
> +		return SYSCLK_66;
> +	case 0x0A:
> +	case 0x08:
> +		return SYSCLK_100;
> +	default:
> +		puts("ERROR: unknown DDR ratio\n");
> +		return SYSCLK_100;
> +	}
> +}
> +
> +unsigned long get_board_ddr_clk(ulong dummy)
> +{
> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> +
> +	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> +	switch (ddr_ratio) {
> +	case 0x0C:
> +	case 0x0A:
> +		return SYSCLK_66;
> +	case 0x08:
> +		return SYSCLK_100;
> +	default:
> +		puts("ERROR: unknown DDR ratio\n");
> +		return SYSCLK_100;
> +	}
> +}
> +
> +#ifdef CONFIG_MMC
> +int board_early_init_f(void)
> +{
> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> +	setbits_be32(&gur->pmuxcr,
> +			(MPC85xx_PMUXCR_SDHC_CD |
> +			 MPC85xx_PMUXCR_SDHC_WP));
> +
> +	/* All the device are enable except for SRIO12 */
> +	setbits_be32(&gur->devdisr, 0x80000);

Add a #define instead of magic 0x80000

> +	return 0;
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> +	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
> +
> +	/*
> +	 * GPIO
> +	 * 0 - 3: CarryBoard Input;
> +	 * 4 - 7: CarryBoard Output;
> +	 * 8 : Mux as SDHC_CD (card detection)
> +	 * 9 : Mux as SDHC_WP
> +	 * 10 : Clear Watchdog timer
> +	 * 11 : LED Input
> +	 * 12 : Output to 1
> +	 * 13 : Open Drain
> +	 * 14 : LED Output
> +	 * 15 : Switch Input
> +	 *
> +	 * Set GPIOs 11, 12, 14 to 1.
> +	 */
> +	out_be32(&pgpio->gpdir, GPIO_DIR);
> +	out_be32(&pgpio->gpodr, GPIO_ODR);
> +	out_be32(&pgpio->gpdat, 0x001A0000);

look at using mpc85xx_gpio.h

> +
> +	puts("Board: Freescale COM Express P2020\n");
> +	return 0;
> +}
> +
> +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
> +
> +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
> +{
> +	u8 data;
> +
> +	if (i2c_read(0x68, reg, 1, &data, 1)) {
> +		M41ST85W_ERROR("unable to read %s bit\n", name);
> +		return;
> +	}
> +
> +	if (data & mask) {
> +		data &= ~mask;
> +		if (i2c_write(0x68, reg, 1, &data, 1)) {
> +			M41ST85W_ERROR("unable to clear %s bit\n", name);
> +			return;
> +		}
> +	}
> +}
> +
> +/*
> + * The P2020COME board has a STMicro M41ST85W RTC/watchdog
> + * at i2c bus 1 address 0x68.
> + */
> +static void start_rtc(void)
> +{
> +	unsigned int bus = i2c_get_bus_num();
> +
> +	if (i2c_set_bus_num(1)) {
> +		M41ST85W_ERROR("unable to set i2c bus\n");
> +		goto out;
> +	}
> +
> +	/* ensure ST (stop) and HT (halt update) bits are cleared */
> +	m41st85w_clear_bit(0x1, 0x80, "ST");
> +	m41st85w_clear_bit(0xc, 0x40, "HT");
> +
> +out:
> +	/* reset the i2c bus */
> +	i2c_set_bus_num(bus);
> +}
> +
> +int board_early_init_r(void)
> +{
> +	start_rtc();
> +	return 0;
> +}
> +
> +void board_reset(void)
> +{
> +	u8 data = (1 << 2) | 0x82;

some #defines instead of magic #s

> +
> +	/* set the hardware watchdog timeout to 1 second, then hang */
> +	i2c_set_bus_num(1);
> +	i2c_write(0x68, 9, 1, &data, 1);
> +
> +	while (1)
> +		/* hang */;
> +}
> +
> +#ifdef CONFIG_TSEC_ENET
> +int board_eth_init(bd_t *bis)
> +{
> +	struct fsl_pq_mdio_info mdio_info;
> +	struct tsec_info_struct tsec_info[4];
> +	int num = 0;
> +
> +#ifdef CONFIG_TSEC1
> +	SET_STD_TSEC_INFO(tsec_info[num], 1);
> +	num++;
> +#endif
> +#ifdef CONFIG_TSEC2
> +	SET_STD_TSEC_INFO(tsec_info[num], 2);
> +	num++;
> +#endif
> +#ifdef CONFIG_TSEC3
> +	SET_STD_TSEC_INFO(tsec_info[num], 3);
> +	if (is_serdes_configured(SGMII_TSEC3)) {
> +		puts("eTSEC3 is in sgmii mode.");
> +		tsec_info[num].flags |= TSEC_SGMII;
> +	}
> +	num++;
> +#endif
> +	if (!num) {
> +		printf("No TSECs initialized\n");
> +		return 0;
> +	}
> +
> +	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
> +	mdio_info.name = DEFAULT_MII_NAME;
> +	fsl_pq_mdio_init(bis, &mdio_info);
> +
> +	tsec_eth_init(bis, tsec_info, num);
> +
> +	return pci_eth_init(bis);
> +}
> +#endif
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +void fdt_fixup_add_2nd_usb(void *blob, int agent)
> +{

What are you trying to do here?

> +	const char *soc_compat = "fsl,p2020-immr";
> +	const char *lbc_compat = "fsl,p2020-elbc";
> +	const u32 *addrcell, *sizecell, *ph;
> +	int off, lbcoff, len, err;
> +	u32 *regbuf = NULL;
> +	u32 *irqbuf = NULL;
> +
> +	off = fdt_node_offset_by_compatible(blob, -1, soc_compat);
> +	if (off < 0) {
> +		printf("WARNING: could not find compatible node %s: %s.\n",
> +			soc_compat, fdt_strerror(off));
> +		return;
> +	}
> +
> +	lbcoff = fdt_node_offset_by_compatible(blob, -1, lbc_compat);
> +	if (lbcoff < 0) {
> +		printf("WARNING: could not find compatible node %s: %s.\n",
> +			lbc_compat, fdt_strerror(lbcoff));
> +		return;
> +	}
> +
> +	addrcell = fdt_getprop(blob, off, "#address-cells", NULL);
> +	sizecell = fdt_getprop(blob, off, "#size-cells", NULL);
> +
> +	off = fdt_add_subnode(blob, off, "usb@23000");
> +	if (off < 0) {
> +		printf("WARNING: could not add 2nd usb node %s.\n",
> +				fdt_strerror(off));
> +		return;
> +	}
> +
> +	err = fdt_setprop_cell(blob, off, "#address-cells", 1);
> +	if (err < 0)
> +		printf("WARNING: could not set #address-cell property: %s\n",
> +			fdt_strerror(err));
> +
> +	err = fdt_setprop_cell(blob, off, "#size-cells", 0);
> +	if (err < 0)
> +		printf("WARNING: could not set #size-cells property: %s\n",
> +			fdt_strerror(err));
> +
> +	err = fdt_setprop_string(blob, off, "compatible", "fsl-usb2-dr");
> +	if (err < 0)
> +		printf("WARNING: could not set compatible property: %s\n",
> +			fdt_strerror(err));
> +
> +	err = fdt_setprop_string(blob, off, "phy_type", "ulpi");
> +	if (err < 0)
> +		printf("WARNING: could not set phy_type property: %s\n",
> +			fdt_strerror(err));
> +
> +	if (agent) {
> +		err = fdt_setprop_string(blob, off, "dr_mode", "peripheral");
> +		if (err < 0)
> +			printf("WARNING: could not set dr_mode property: %s\n",
> +				fdt_strerror(err));
> +	}
> +
> +	if (addrcell && *addrcell == 2) {
> +		regbuf[0] = 0;
> +		regbuf[1] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
> +		len = 2;
> +	} else {
> +		regbuf[0] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
> +		len = 1;
> +	}
> +
> +	if (sizecell && *sizecell == 2) {
> +		regbuf[len] = 0;
> +		regbuf[len + 1] = 0x1000;
> +		len = 2;
> +	} else {
> +		regbuf[len] = 0x1000;
> +		len++;
> +	}
> +
> +	err = fdt_setprop(blob, off, "reg", regbuf, len * sizeof(u32));
> +	if (err < 0)
> +		printf("WARNING: could not set <%s> %s\n",
> +					"reg", fdt_strerror(err));
> +
> +	irqbuf[0] = 0x2e;
> +	irqbuf[1] = 0x2;
> +
> +	err = fdt_setprop(blob, off, "interrupts", irqbuf, 2 * sizeof(u32));
> +	if (err < 0)
> +		printf("WARNING: could not set %s %s\n",
> +				"interrupts", fdt_strerror(err));
> +
> +	ph = fdt_getprop(blob, lbcoff, "interrupt-parent", 0);
> +	if (!ph) {
> +		printf("WARNING: could not read interrupt-parent property\n");
> +		return;
> +	}
> +
> +	err = fdt_setprop(blob, off, "interrupt-parent", ph, sizeof(u32));
> +	if (err < 0)
> +		printf("WARNING: could not set %s %s\n",
> +				"interrupt-parent", fdt_strerror(err));
> +}
> +
> +void ft_board_setup(void *blob, bd_t *bd)
> +{
> +	phys_addr_t base;
> +	phys_size_t size;
> +	int agent;
> +
> +	ft_cpu_setup(blob, bd);
> +
> +	base = getenv_bootm_low();
> +	size = getenv_bootm_size();
> +
> +#if defined(CONFIG_PCI)
> +	ft_pci_board_setup(blob);
> +#endif
> +
> +	fdt_fixup_memory(blob, (u64)base, (u64)size);
> +
> +	if (!hwconfig("usb2"))
> +		return;
> +
> +	agent = hwconfig_subarg_cmp("usb2", "dr_mode", "peripheral");
> +
> +	/*
> +	 * Add the 2nd usb node and enable it. eLBC will
> +	 * now be disabled since it is MUXed with USB2
> +	 */
> +
> +	fdt_fixup_add_2nd_usb(blob, agent);
> +}
> +#endif
> diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
> new file mode 100644
> index 0000000..e1dd056
> --- /dev/null
> +++ b/board/freescale/p2020come/tlb.c
> @@ -0,0 +1,100 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/mmu.h>
> +

For any regions that do NOT have code, we should remove MAS3_SX bit:

> +struct fsl_e_tlb_entry tlb_table[] = {
> +	/* TLB 0 - for temp stack in cache */
> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> +			0, 0, BOOKE_PAGESZ_4K, 0),
> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> +			0, 0, BOOKE_PAGESZ_4K, 0),
> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> +			0, 0, BOOKE_PAGESZ_4K, 0),
> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> +			0, 0, BOOKE_PAGESZ_4K, 0),
> +
> +	/* TLB 1 */
> +	/* *I*** - Covers boot page */
> +	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 0, BOOKE_PAGESZ_4K, 1),
> +
> +	/* *I*G* - CCSRBAR */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 1, BOOKE_PAGESZ_1M, 1),
> +
> +#if defined(CONFIG_PCI)
> +	/* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 2, BOOKE_PAGESZ_1G, 1),
> +
> +	/* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 3, BOOKE_PAGESZ_256M, 1),
> +
> +
> +	/* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
> +			CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 4, BOOKE_PAGESZ_256M, 1),
> +
> +	/*
> +	 * *I*G* - PCI I/O
> +	 *
> +	 * PCI3 => 0xFFC10000
> +	 * PCI2 => 0xFFC2,0000
> +	 * PCI1 => 0xFFC3,0000
> +	 */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 5, BOOKE_PAGESZ_256K, 1),
> +#endif /* #if defined(CONFIG_PCI) */
> +
> +#if defined(CONFIG_SYS_RAMBOOT)
> +	/* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 6, BOOKE_PAGESZ_1G, 1),
> +
> +	/*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
> +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> +			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> +			0, 7, BOOKE_PAGESZ_1G, 1),
> +#endif
> +};
> +
> +int num_tlb_entries = ARRAY_SIZE(tlb_table);

On Fri, Nov 11, 2011 at 07:22:14AM -0600, Kumar Gala wrote:
> 
> On Nov 10, 2011, at 3:11 PM, Ira W. Snyder wrote:
> 
> > This adds support for the Freescale COM Express P2020 board. This board
> > is similar to the P1_P2_RDB, but has some extra (as well as missing)
> > peripherals.
> > 
> > Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
> > Using the HRESET_REQ register does not work.
> > 
> > This board has no NOR flash, and can only be booted via SD or SPI. This
> > procedure is documented in Freescale Document Number AN3659 "Booting
> > from On-Chip RAM (eSDHC or eSPI)." Some alternative documentation is
> > provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
> > Processor Reference Manual" (section 4.5).
> > 
> > Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
> > ---
> > 
> 
> 
> > diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
> > new file mode 100644
> > index 0000000..dd2a4dd
> > --- /dev/null
> > +++ b/board/freescale/p2020come/ddr.c
> > @@ -0,0 +1,245 @@
> > +/*
> > + * Copyright 2009, 2011 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/mmu.h>
> > +#include <asm/immap_85xx.h>
> > +#include <asm/processor.h>
> > +#include <asm/fsl_ddr_sdram.h>
> > +#include <asm/io.h>
> > +#include <asm/fsl_law.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
> > +#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
> > +#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
> > +#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
> > +#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
> > +#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
> > +#define CONFIG_SYS_DDR_ZQ_CONTROL	0x00000000
> > +#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x00000000
> > +#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
> > +#define CONFIG_SYS_DDR_RCW_1		0x00000000
> > +#define CONFIG_SYS_DDR_RCW_2		0x00000000
> > +#define CONFIG_SYS_DDR_CONTROL		0x43000000	/* Type = DDR2*/
> > +#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
> > +#define CONFIG_SYS_DDR_TIMING_4		0x00000000
> > +#define CONFIG_SYS_DDR_TIMING_5		0x00000000
> > +
> > +#define CONFIG_SYS_DDR_TIMING_3_400	0x00010000
> > +#define CONFIG_SYS_DDR_TIMING_0_400	0x00260802
> > +#define CONFIG_SYS_DDR_TIMING_1_400	0x39355322
> > +#define CONFIG_SYS_DDR_TIMING_2_400	0x1f9048ca
> > +#define CONFIG_SYS_DDR_CLK_CTRL_400	0x02800000
> > +#define CONFIG_SYS_DDR_MODE_1_400	0x00480432
> > +#define CONFIG_SYS_DDR_MODE_2_400	0x00000000
> > +#define CONFIG_SYS_DDR_INTERVAL_400	0x06180100
> > +
> > +#define CONFIG_SYS_DDR_TIMING_3_533	0x00020000
> > +#define CONFIG_SYS_DDR_TIMING_0_533	0x00260802
> > +#define CONFIG_SYS_DDR_TIMING_1_533	0x4c47c432
> > +#define CONFIG_SYS_DDR_TIMING_2_533	0x0f9848ce
> > +#define CONFIG_SYS_DDR_CLK_CTRL_533	0x02800000
> > +#define CONFIG_SYS_DDR_MODE_1_533	0x00040642
> > +#define CONFIG_SYS_DDR_MODE_2_533	0x00000000
> > +#define CONFIG_SYS_DDR_INTERVAL_533	0x08200100
> > +
> > +#define CONFIG_SYS_DDR_TIMING_3_667	0x00030000
> > +#define CONFIG_SYS_DDR_TIMING_0_667	0x55770802
> > +#define CONFIG_SYS_DDR_TIMING_1_667	0x5f599543
> > +#define CONFIG_SYS_DDR_TIMING_2_667	0x0fa074d1
> > +#define CONFIG_SYS_DDR_CLK_CTRL_667	0x03000000
> > +#define CONFIG_SYS_DDR_MODE_1_667	0x00040852
> > +#define CONFIG_SYS_DDR_MODE_2_667	0x00000000
> > +#define CONFIG_SYS_DDR_INTERVAL_667	0x0a280100
> > +
> > +#define CONFIG_SYS_DDR_TIMING_3_800	0x00040000
> > +#define CONFIG_SYS_DDR_TIMING_0_800	0x00770802
> > +#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b6543
> > +#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa074d1
> > +#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
> > +#define CONFIG_SYS_DDR_MODE_1_800	0x00040852
> > +#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
> > +#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
> > +
> > +fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
> > +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> > +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> > +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> > +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
> > +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
> > +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
> > +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
> > +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> > +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> > +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
> > +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
> > +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> > +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
> > +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> > +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
> > +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> > +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> > +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> > +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> > +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> > +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> > +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> > +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> > +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> > +};
> > +
> > +fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
> > +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> > +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> > +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> > +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
> > +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
> > +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
> > +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
> > +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> > +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> > +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
> > +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
> > +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> > +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
> > +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> > +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
> > +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> > +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> > +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> > +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> > +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> > +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> > +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> > +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> > +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> > +};
> > +
> > +fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
> > +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> > +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> > +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> > +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
> > +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
> > +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
> > +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
> > +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> > +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> > +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
> > +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
> > +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> > +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
> > +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> > +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
> > +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> > +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> > +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> > +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> > +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> > +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> > +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> > +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> > +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> > +};
> > +
> > +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
> > +	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
> > +	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
> > +	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
> > +	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
> > +	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
> > +	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
> > +	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
> > +	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
> > +	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
> > +	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
> > +	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
> > +	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
> > +	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
> > +	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
> > +	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
> > +	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
> > +	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
> > +	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
> > +	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
> > +	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
> > +	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
> > +	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
> > +	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
> > +	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
> > +};
> > +
> > +/*
> > + * Fixed sdram init -- doesn't use serial presence detect.
> > + */
> > +
> > +phys_size_t fixed_sdram(void)
> > +{
> > +	char buf[32];
> > +	fsl_ddr_cfg_regs_t ddr_cfg_regs;
> > +	size_t ddr_size;
> > +	struct cpu_type *cpu;
> > +	ulong ddr_freq, ddr_freq_mhz;
> > +
> > +	cpu = gd->cpu;
> > +	/* P1020 and it's derivatives support max 32bit DDR width */
> > +	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
> > +		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
> > +		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
> 
> These checks don't make sense if you are a P2020 SoC
> 

This entire file is identical to board/freescale/p1_p2_rdb/ddr.c. In
fact, since this board only boots via the On-Chip ROM, the whole file is
useless: fixed_sdram() should just return the RAM size. We're running
from RAM when this function executes.

Is it ok with you if I replace the entire file with the following?

phys_size_t fixed_sdram(void)
{
	return CONFIG_SYS_SDRAM_SIZE << 20;
}

> > +	} else {
> > +		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> > +	}
> > +#if defined(CONFIG_SYS_RAMBOOT)
> > +	return ddr_size;
> > +#endif
> > +	ddr_freq = get_ddr_freq(0);
> > +	ddr_freq_mhz = ddr_freq / 1000000;
> > +
> > +	printf("Configuring DDR for %s MT/s data rate\n",
> > +				strmhz(buf, ddr_freq));
> > +
> > +	if (ddr_freq_mhz <= 400)
> > +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
> > +	else if (ddr_freq_mhz <= 533)
> > +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
> > +	else if (ddr_freq_mhz <= 667)
> > +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
> > +	else if (ddr_freq_mhz <= 800)
> > +		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
> > +	else
> > +		panic("Unsupported DDR data rate %s MT/s data rate\n",
> > +					strmhz(buf, ddr_freq));
> 
> Does the board really support different DDR freq or is this copy / paste?
> 

The memory is an SODIMM, but the RAM is configured before U-Boot runs by
the Freescale On-Chip ROM. See above comment.

> > +
> > +	/* P1020 and it's derivatives support max 32bit DDR width */
> > +	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
> > +		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
> > +		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
> > +		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
> > +	}
> 
> Same comment as above
> 
> > +
> > +	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
> > +
> > +	set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
> > +	return ddr_size;
> > +}
> > diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
> > new file mode 100644
> > index 0000000..56508db
> > --- /dev/null
> > +++ b/board/freescale/p2020come/law.c
> > @@ -0,0 +1,36 @@
> > +/*
> > + * Copyright 2009 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/fsl_law.h>
> > +#include <asm/mmu.h>
> > +
> > +struct law_entry law_table[] = {
> > +	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> > +	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> > +	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
> > +	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
> > +	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
> > +	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
> 
> We normally set these up dynamically.
> 

This is a modified version of the code from
board/freescale/p1_p2_rdb/law.c. Can you suggest an in tree example of
the way you'd like the code to look? I copied what I assume is a good
example...

> > +};
> > +
> > +int num_law_entries = ARRAY_SIZE(law_table);
> > diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
> > new file mode 100644
> > index 0000000..2e334cf
> > --- /dev/null
> > +++ b/board/freescale/p2020come/p2020come.c
> > @@ -0,0 +1,401 @@
> > +/*
> > + * Copyright 2009 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <hwconfig.h>
> > +#include <command.h>
> > +#include <asm/processor.h>
> > +#include <asm/mmu.h>
> > +#include <asm/cache.h>
> > +#include <asm/immap_85xx.h>
> > +#include <asm/fsl_serdes.h>
> > +#include <asm/io.h>
> > +#include <miiphy.h>
> > +#include <libfdt.h>
> > +#include <fdt_support.h>
> > +#include <fsl_mdio.h>
> > +#include <tsec.h>
> > +#include <vsc7385.h>
> > +#include <netdev.h>
> > +#include <mmc.h>
> > +#include <malloc.h>
> > +#include <i2c.h>
> > +
> > +#if defined(CONFIG_PCI)
> > +#include <asm/fsl_pci.h>
> > +#include <pci.h>
> > +#endif
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#if defined(CONFIG_PCI)
> > +void pci_init_board(void)
> > +{
> > +	fsl_pcie_init_board(0);
> > +}
> > +
> > +void ft_pci_board_setup(void *blob)
> > +{
> > +	FT_FSL_PCI_SETUP;
> > +}
> > +#endif
> > +
> > +/*
> > + * GPIO
> > + * 0 - 3: CarryBoard Input;
> > + * 4 - 7: CarryBoard Output;
> > + * 8 : Mux as SDHC_CD (card detection)
> > + * 9 : Mux as SDHC_WP
> > + * 10 : Clear Watchdog timer
> > + * 11 : LED Input
> > + * 12 : Output to 1
> > + * 13 : Open Drain
> > + * 14 : LED Output
> > + * 15 : Switch Input
> > + */
> > +#define GPIO_DIR		0x0f3a0000
> > +#define GPIO_ODR		0x00000000
> > +
> > +#define BOARD_PERI_RST_SET	(VSC7385_RST_SET | SLIC_RST_SET | \
> > +				 SGMII_PHY_RST_SET | PCIE_RST_SET | \
> > +				 RGMII_PHY_RST_SET)
> > +
> > +#define SYSCLK_MASK	0x00200000
> > +#define BOARDREV_MASK	0x10100000
> > +#define BOARDREV_B	0x10100000
> > +#define BOARDREV_C	0x00100000
> > +#define BOARDREV_D	0x00000000
> > +
> > +#define SYSCLK_66	66666666
> > +#define SYSCLK_50	50000000
> > +#define SYSCLK_100	100000000
> > +
> > +unsigned long get_board_sys_clk(ulong dummy)
> > +{
> > +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > +	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> > +
> > +	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> > +	switch (ddr_ratio) {
> > +	case 0x0C:
> > +		return SYSCLK_66;
> > +	case 0x0A:
> > +	case 0x08:
> > +		return SYSCLK_100;
> > +	default:
> > +		puts("ERROR: unknown DDR ratio\n");
> > +		return SYSCLK_100;
> > +	}
> > +}
> > +
> > +unsigned long get_board_ddr_clk(ulong dummy)
> > +{
> > +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > +	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
> > +
> > +	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
> > +	switch (ddr_ratio) {
> > +	case 0x0C:
> > +	case 0x0A:
> > +		return SYSCLK_66;
> > +	case 0x08:
> > +		return SYSCLK_100;
> > +	default:
> > +		puts("ERROR: unknown DDR ratio\n");
> > +		return SYSCLK_100;
> > +	}
> > +}
> > +
> > +#ifdef CONFIG_MMC
> > +int board_early_init_f(void)
> > +{
> > +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > +
> > +	setbits_be32(&gur->pmuxcr,
> > +			(MPC85xx_PMUXCR_SDHC_CD |
> > +			 MPC85xx_PMUXCR_SDHC_WP));
> > +
> > +	/* All the device are enable except for SRIO12 */
> > +	setbits_be32(&gur->devdisr, 0x80000);
> 
> Add a #define instead of magic 0x80000
> 
> > +	return 0;
> > +}
> > +#endif
> > +
> > +int checkboard(void)
> > +{
> > +	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
> > +
> > +	/*
> > +	 * GPIO
> > +	 * 0 - 3: CarryBoard Input;
> > +	 * 4 - 7: CarryBoard Output;
> > +	 * 8 : Mux as SDHC_CD (card detection)
> > +	 * 9 : Mux as SDHC_WP
> > +	 * 10 : Clear Watchdog timer
> > +	 * 11 : LED Input
> > +	 * 12 : Output to 1
> > +	 * 13 : Open Drain
> > +	 * 14 : LED Output
> > +	 * 15 : Switch Input
> > +	 *
> > +	 * Set GPIOs 11, 12, 14 to 1.
> > +	 */
> > +	out_be32(&pgpio->gpdir, GPIO_DIR);
> > +	out_be32(&pgpio->gpodr, GPIO_ODR);
> > +	out_be32(&pgpio->gpdat, 0x001A0000);
> 
> look at using mpc85xx_gpio.h
> 

Ok. This was copied from the BSP code. I'll change it to use the
mpc85xx_gpio code.

While we're here, perhaps you can get the schematic for this board and
see what the GPIO's are actually connected to. I can't get the
schematic, so these comments are copied from the BSP code.

The ones labeled "LED" (11 and 14) don't appear to change any LEDs that
I can see on the board.

> > +
> > +	puts("Board: Freescale COM Express P2020\n");
> > +	return 0;
> > +}
> > +
> > +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
> > +
> > +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
> > +{
> > +	u8 data;
> > +
> > +	if (i2c_read(0x68, reg, 1, &data, 1)) {
> > +		M41ST85W_ERROR("unable to read %s bit\n", name);
> > +		return;
> > +	}
> > +
> > +	if (data & mask) {
> > +		data &= ~mask;
> > +		if (i2c_write(0x68, reg, 1, &data, 1)) {
> > +			M41ST85W_ERROR("unable to clear %s bit\n", name);
> > +			return;
> > +		}
> > +	}
> > +}
> > +
> > +/*
> > + * The P2020COME board has a STMicro M41ST85W RTC/watchdog
> > + * at i2c bus 1 address 0x68.
> > + */
> > +static void start_rtc(void)
> > +{
> > +	unsigned int bus = i2c_get_bus_num();
> > +
> > +	if (i2c_set_bus_num(1)) {
> > +		M41ST85W_ERROR("unable to set i2c bus\n");
> > +		goto out;
> > +	}
> > +
> > +	/* ensure ST (stop) and HT (halt update) bits are cleared */
> > +	m41st85w_clear_bit(0x1, 0x80, "ST");
> > +	m41st85w_clear_bit(0xc, 0x40, "HT");
> > +
> > +out:
> > +	/* reset the i2c bus */
> > +	i2c_set_bus_num(bus);
> > +}
> > +
> > +int board_early_init_r(void)
> > +{
> > +	start_rtc();
> > +	return 0;
> > +}
> > +
> > +void board_reset(void)
> > +{
> > +	u8 data = (1 << 2) | 0x82;
> 
> some #defines instead of magic #s
> 
> > +
> > +	/* set the hardware watchdog timeout to 1 second, then hang */
> > +	i2c_set_bus_num(1);
> > +	i2c_write(0x68, 9, 1, &data, 1);
> > +
> > +	while (1)
> > +		/* hang */;
> > +}
> > +
> > +#ifdef CONFIG_TSEC_ENET
> > +int board_eth_init(bd_t *bis)
> > +{
> > +	struct fsl_pq_mdio_info mdio_info;
> > +	struct tsec_info_struct tsec_info[4];
> > +	int num = 0;
> > +
> > +#ifdef CONFIG_TSEC1
> > +	SET_STD_TSEC_INFO(tsec_info[num], 1);
> > +	num++;
> > +#endif
> > +#ifdef CONFIG_TSEC2
> > +	SET_STD_TSEC_INFO(tsec_info[num], 2);
> > +	num++;
> > +#endif
> > +#ifdef CONFIG_TSEC3
> > +	SET_STD_TSEC_INFO(tsec_info[num], 3);
> > +	if (is_serdes_configured(SGMII_TSEC3)) {
> > +		puts("eTSEC3 is in sgmii mode.");
> > +		tsec_info[num].flags |= TSEC_SGMII;
> > +	}
> > +	num++;
> > +#endif
> > +	if (!num) {
> > +		printf("No TSECs initialized\n");
> > +		return 0;
> > +	}
> > +
> > +	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
> > +	mdio_info.name = DEFAULT_MII_NAME;
> > +	fsl_pq_mdio_init(bis, &mdio_info);
> > +
> > +	tsec_eth_init(bis, tsec_info, num);
> > +
> > +	return pci_eth_init(bis);
> > +}
> > +#endif
> > +
> > +#if defined(CONFIG_OF_BOARD_SETUP)
> > +void fdt_fixup_add_2nd_usb(void *blob, int agent)
> > +{
> 
> What are you trying to do here?
> 

This was copied from the BSP code, I have no idea what the purpose is. I
just checked: the board works fine with this removed. I'll remove it.

> > +	const char *soc_compat = "fsl,p2020-immr";
> > +	const char *lbc_compat = "fsl,p2020-elbc";
> > +	const u32 *addrcell, *sizecell, *ph;
> > +	int off, lbcoff, len, err;
> > +	u32 *regbuf = NULL;
> > +	u32 *irqbuf = NULL;
> > +
> > +	off = fdt_node_offset_by_compatible(blob, -1, soc_compat);
> > +	if (off < 0) {
> > +		printf("WARNING: could not find compatible node %s: %s.\n",
> > +			soc_compat, fdt_strerror(off));
> > +		return;
> > +	}
> > +
> > +	lbcoff = fdt_node_offset_by_compatible(blob, -1, lbc_compat);
> > +	if (lbcoff < 0) {
> > +		printf("WARNING: could not find compatible node %s: %s.\n",
> > +			lbc_compat, fdt_strerror(lbcoff));
> > +		return;
> > +	}
> > +
> > +	addrcell = fdt_getprop(blob, off, "#address-cells", NULL);
> > +	sizecell = fdt_getprop(blob, off, "#size-cells", NULL);
> > +
> > +	off = fdt_add_subnode(blob, off, "usb@23000");
> > +	if (off < 0) {
> > +		printf("WARNING: could not add 2nd usb node %s.\n",
> > +				fdt_strerror(off));
> > +		return;
> > +	}
> > +
> > +	err = fdt_setprop_cell(blob, off, "#address-cells", 1);
> > +	if (err < 0)
> > +		printf("WARNING: could not set #address-cell property: %s\n",
> > +			fdt_strerror(err));
> > +
> > +	err = fdt_setprop_cell(blob, off, "#size-cells", 0);
> > +	if (err < 0)
> > +		printf("WARNING: could not set #size-cells property: %s\n",
> > +			fdt_strerror(err));
> > +
> > +	err = fdt_setprop_string(blob, off, "compatible", "fsl-usb2-dr");
> > +	if (err < 0)
> > +		printf("WARNING: could not set compatible property: %s\n",
> > +			fdt_strerror(err));
> > +
> > +	err = fdt_setprop_string(blob, off, "phy_type", "ulpi");
> > +	if (err < 0)
> > +		printf("WARNING: could not set phy_type property: %s\n",
> > +			fdt_strerror(err));
> > +
> > +	if (agent) {
> > +		err = fdt_setprop_string(blob, off, "dr_mode", "peripheral");
> > +		if (err < 0)
> > +			printf("WARNING: could not set dr_mode property: %s\n",
> > +				fdt_strerror(err));
> > +	}
> > +
> > +	if (addrcell && *addrcell == 2) {
> > +		regbuf[0] = 0;
> > +		regbuf[1] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
> > +		len = 2;
> > +	} else {
> > +		regbuf[0] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
> > +		len = 1;
> > +	}
> > +
> > +	if (sizecell && *sizecell == 2) {
> > +		regbuf[len] = 0;
> > +		regbuf[len + 1] = 0x1000;
> > +		len = 2;
> > +	} else {
> > +		regbuf[len] = 0x1000;
> > +		len++;
> > +	}
> > +
> > +	err = fdt_setprop(blob, off, "reg", regbuf, len * sizeof(u32));
> > +	if (err < 0)
> > +		printf("WARNING: could not set <%s> %s\n",
> > +					"reg", fdt_strerror(err));
> > +
> > +	irqbuf[0] = 0x2e;
> > +	irqbuf[1] = 0x2;
> > +
> > +	err = fdt_setprop(blob, off, "interrupts", irqbuf, 2 * sizeof(u32));
> > +	if (err < 0)
> > +		printf("WARNING: could not set %s %s\n",
> > +				"interrupts", fdt_strerror(err));
> > +
> > +	ph = fdt_getprop(blob, lbcoff, "interrupt-parent", 0);
> > +	if (!ph) {
> > +		printf("WARNING: could not read interrupt-parent property\n");
> > +		return;
> > +	}
> > +
> > +	err = fdt_setprop(blob, off, "interrupt-parent", ph, sizeof(u32));
> > +	if (err < 0)
> > +		printf("WARNING: could not set %s %s\n",
> > +				"interrupt-parent", fdt_strerror(err));
> > +}
> > +
> > +void ft_board_setup(void *blob, bd_t *bd)
> > +{
> > +	phys_addr_t base;
> > +	phys_size_t size;
> > +	int agent;
> > +
> > +	ft_cpu_setup(blob, bd);
> > +
> > +	base = getenv_bootm_low();
> > +	size = getenv_bootm_size();
> > +
> > +#if defined(CONFIG_PCI)
> > +	ft_pci_board_setup(blob);
> > +#endif
> > +
> > +	fdt_fixup_memory(blob, (u64)base, (u64)size);
> > +
> > +	if (!hwconfig("usb2"))
> > +		return;
> > +
> > +	agent = hwconfig_subarg_cmp("usb2", "dr_mode", "peripheral");
> > +
> > +	/*
> > +	 * Add the 2nd usb node and enable it. eLBC will
> > +	 * now be disabled since it is MUXed with USB2
> > +	 */
> > +
> > +	fdt_fixup_add_2nd_usb(blob, agent);
> > +}
> > +#endif
> > diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
> > new file mode 100644
> > index 0000000..e1dd056
> > --- /dev/null
> > +++ b/board/freescale/p2020come/tlb.c
> > @@ -0,0 +1,100 @@
> > +/*
> > + * Copyright 2011 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/mmu.h>
> > +
> 
> For any regions that do NOT have code, we should remove MAS3_SX bit:
> 

I assume you mean the CCSR and PCI regions. Maybe the
CONFIG_SYS_INIT_RAM_ADDR regions too, I don't know what they're used
for.

Thanks for the comments. I look forward to your feedback on the couple
of questions I have.

Ira

> > +struct fsl_e_tlb_entry tlb_table[] = {
> > +	/* TLB 0 - for temp stack in cache */
> > +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
> > +			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > +			0, 0, BOOKE_PAGESZ_4K, 0),
> > +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
> > +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > +			0, 0, BOOKE_PAGESZ_4K, 0),
> > +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
> > +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > +			0, 0, BOOKE_PAGESZ_4K, 0),
> > +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
> > +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> > +			0, 0, BOOKE_PAGESZ_4K, 0),
> > +
> > +	/* TLB 1 */
> > +	/* *I*** - Covers boot page */
> > +	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 0, BOOKE_PAGESZ_4K, 1),
> > +
> > +	/* *I*G* - CCSRBAR */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 1, BOOKE_PAGESZ_1M, 1),
> > +
> > +#if defined(CONFIG_PCI)
> > +	/* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 2, BOOKE_PAGESZ_1G, 1),
> > +
> > +	/* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 3, BOOKE_PAGESZ_256M, 1),
> > +
> > +
> > +	/* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
> > +			CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 4, BOOKE_PAGESZ_256M, 1),
> > +
> > +	/*
> > +	 * *I*G* - PCI I/O
> > +	 *
> > +	 * PCI3 => 0xFFC10000
> > +	 * PCI2 => 0xFFC2,0000
> > +	 * PCI1 => 0xFFC3,0000
> > +	 */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 5, BOOKE_PAGESZ_256K, 1),
> > +#endif /* #if defined(CONFIG_PCI) */
> > +
> > +#if defined(CONFIG_SYS_RAMBOOT)
> > +	/* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 6, BOOKE_PAGESZ_1G, 1),
> > +
> > +	/*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
> > +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> > +			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
> > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> > +			0, 7, BOOKE_PAGESZ_1G, 1),
> > +#endif
> > +};
> > +
> > +int num_tlb_entries = ARRAY_SIZE(tlb_table);
> 
>

On Fri, Nov 11, 2011 at 10:53 AM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
>> Does the board really support different DDR freq or is this copy / paste?
>>
>
> The memory is an SODIMM, but the RAM is configured before U-Boot runs by
> the Freescale On-Chip ROM. See above comment.

If this is a P2020 you could use the on chip rom to copy u-boot to
L2SRAM and configure DDR via SPD - if you ever plan to change the
SODIMMs this could be very useful.

-M

On Fri, Nov 11, 2011 at 04:58:17PM +0000, McClintock Matthew-B29882 wrote:
> On Fri, Nov 11, 2011 at 10:53 AM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> >> Does the board really support different DDR freq or is this copy / paste?
> >>
> >
> > The memory is an SODIMM, but the RAM is configured before U-Boot runs by
> > the Freescale On-Chip ROM. See above comment.
> 
> If this is a P2020 you could use the on chip rom to copy u-boot to
> L2SRAM and configure DDR via SPD - if you ever plan to change the
> SODIMMs this could be very useful.
> 

Yep, this is a P2020.

I'll check the Freescale documentation. Hopefully it provides an example
of how to configure the On-Chip ROM to use L2SRAM instead of DDR.

I'll try and find a U-Boot port that configures DDR via SPD. I'm sure
there are plenty, however any hints are welcome. :)

Thanks for the input,
Ira

On Fri, Nov 11, 2011 at 11:12 AM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> Yep, this is a P2020.
>
> I'll check the Freescale documentation. Hopefully it provides an example
> of how to configure the On-Chip ROM to use L2SRAM instead of DDR.
>
> I'll try and find a U-Boot port that configures DDR via SPD. I'm sure
> there are plenty, however any hints are welcome. :)

For an example the P2020DS works like this... I've attached the
boot-format dat file as well.

-M

On Fri, Nov 11, 2011 at 08:36:47PM +0000, McClintock Matthew-B29882 wrote:
> On Fri, Nov 11, 2011 at 11:12 AM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > Yep, this is a P2020.
> >
> > I'll check the Freescale documentation. Hopefully it provides an example
> > of how to configure the On-Chip ROM to use L2SRAM instead of DDR.
> >
> > I'll try and find a U-Boot port that configures DDR via SPD. I'm sure
> > there are plenty, however any hints are welcome. :)
> 
> For an example the P2020DS works like this... I've attached the
> boot-format dat file as well.
> 

Thanks. That config_sram.dat is exactly what I came up with.

I have my board booting via L2SRAM, but the DDR doesn't get configured
correctly yet. I'm trying to figure out how the DDR SPD stuff works in
U-Boot. I've never used it before. I'm following the P2020DS code as an
example, but I haven't yet figured out how the code in
board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
structure especially).

Ira

On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> Thanks. That config_sram.dat is exactly what I came up with.
>
> I have my board booting via L2SRAM, but the DDR doesn't get configured
> correctly yet. I'm trying to figure out how the DDR SPD stuff works in
> U-Boot. I've never used it before. I'm following the P2020DS code as an
> example, but I haven't yet figured out how the code in
> board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
> structure especially).

If you board has i2c to the ddr modules it should be able to use the
timing info from there. I think CONFIG_DDR_SPD is the config option
you are looking for. I know the P2020DS does SPD from L2SRAM.

-M

On Fri, Nov 11, 2011 at 09:07:23PM +0000, McClintock Matthew-B29882 wrote:
> On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > Thanks. That config_sram.dat is exactly what I came up with.
> >
> > I have my board booting via L2SRAM, but the DDR doesn't get configured
> > correctly yet. I'm trying to figure out how the DDR SPD stuff works in
> > U-Boot. I've never used it before. I'm following the P2020DS code as an
> > example, but I haven't yet figured out how the code in
> > board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
> > structure especially).
> 
> If you board has i2c to the ddr modules it should be able to use the
> timing info from there. I think CONFIG_DDR_SPD is the config option
> you are looking for. I know the P2020DS does SPD from L2SRAM.
> 

The only thing that looks like an SPD chip is at i2c bus 1, address
0x53. I setup my board configuration with:

#define CONFIG_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_CHIP_SELECTS_PER_CTRL	2
#define CONFIG_SYS_DDR_SBE		0x00010000

#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM		1
#define SPD_EEPROM_ADDRESS		0x53

Some of the settings the SPD code computes are correct, and some are
completely wrong. I can't figure out how to make this work.

Here is the raw SPD dumped from a working U-Boot:

0000: 92 10 0b 08 02 11 00 09 0b 52 01 08 0c 00 3e 00    .........R....>.
0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 05    ixi0i. .p.<<....
0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 1f 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 01 94 01 10 25 03 ae 48 48 e3 e3    .........%..HH..
0080: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32    SG572568EMR069S2
0090: 53 46 00 00 80 ce 53 4d 41 52 54 4d 6f 64 75 6c    SF....SMARTModul
00a0: 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    arTechnologies..
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

And here is the output of an interactive FSL DDR run:

U-Boot 2011.09-00929-g3b5f71c-dirty (Nov 11 2011 - 13:31:13)

CPU0:  P2020E, Version: 2.0, (0x80ea0020)
Core:  E500, Version: 5.0, (0x80211050)
Clock Configuration:
       CPU0:1200 MHz, CPU1:1200 MHz, 
       CCB:600  MHz,
       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: Freescale COM Express P2020
I2C:   ready
SPI:   ready
DRAM:  FSL DDR>
FSL DDR>
FSL DDR>compute
unknown module_type 0x08
Detected UDIMM SG572568EMR069S2SF
The choosen cas latency 16 is too large
FSL DDR>print c0 d0
SPD info:  Controller=0 DIMM=0
0      : 92 info_size_crc  bytes written into serial memory, CRC coverage
1      : 10 spd_rev        SPD Revision
2      : 0b mem_type       Key Byte / DRAM Device Type
3      : 08 module_type    Key Byte / Module Type
4      : 02 density_banks  SDRAM Density and Banks
5      : 11 addressing     SDRAM Addressing
6      : 00 module_vdd     Module Nominal Voltage, VDD
7      : 09 organization   Module Organization
8      : 0b bus_width      Module Memory Bus Width
9      : 52 ftb_div        Fine Timebase (FTB) Dividend / Divisor
10     : 01 mtb_dividend   Medium Timebase (MTB) Dividend
11     : 08 mtb_divisor    Medium Timebase (MTB) Divisor
12     : 0c tCK_min        SDRAM Minimum Cycle Time
13     : 00 res_13         Reserved
14     : 3e caslat_lsb     CAS Latencies Supported, LSB
15     : 00 caslat_msb     CAS Latencies Supported, MSB
16     : 69 tAA_min        Min CAS Latency Time
17     : 78 tWR_min        Min Write REcovery Time
18     : 69 tRCD_min       Min RAS# to CAS# Delay Time
19     : 30 tRRD_min       Min Row Active to Row Active Delay Time
20     : 69 tRP_min        Min Row Precharge Delay Time
21     : 11 tRAS_tRC_ext   Upper Nibbles for tRAS and tRC
22     : 20 tRAS_min_lsb   Min Active to Precharge Delay Time, LSB
23     : 89 tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB
24     : 70 tRFC_min_lsb   Min Refresh Recovery Delay Time LSB
25     : 03 tRFC_min_msb   Min Refresh Recovery Delay Time MSB
26     : 3c tWTR_min       Min Internal Write to Read Command Delay Time
27     : 3c tRTP_min Min Internal Read to Precharge Command Delay Time
28     : 00 tFAW_msb       Upper Nibble for tFAW
29     : f0 tFAW_min       Min Four Activate Window Delay Time
30     : 83 opt_features   SDRAM Optional Features
31     : 05 therm_ref_opt  SDRAM Thermal and Refresh Opts
32     : 80 therm_sensor  SDRAM Thermal Sensor
33     : 00 device_type  SDRAM Device Type
34 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
60 -116: 0f111f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000117    : 01 Module MfgID Code LSB - JEP-106
118    : 94 Module MfgID Code MSB - JEP-106
119    : 01 Mfg Location
120-121: 10 25 Mfg Date
122-125: 03 ae 48 48    Module Serial Number
126-127: e3 e3   SPD CRC
128-145: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 53 46    Mfg's Module Part Number
146-147: 00 00 Module Revision code
148    : 80 DRAM MfgID Code LSB - JEP-106
149    : ce DRAM MfgID Code MSB - JEP-106
150-175: 53 4d 41 52 54 4d 6f 64 75 6c 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    Mfg's Specific Data
176-255: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000   Mfg's Specific Data



DIMM parameters:  Controller=0 DIMM=0
DIMM organization parameters:
module part name = SG572568EMR069S2SF
rank_density = 1073741824 bytes (1024 megabytes)
capacity = 2147483648 bytes (2048 megabytes)
burst_lengths_bitmask = 00
base_addresss = 0 (00000000 00000000)
n_ranks = 2
data_width = 72
primary_sdram_width = 64
ec_sdram_width = 8
registered_dimm = 0
n_row_addr = 0
n_col_addr = 0
edc_config = 0
n_banks_per_sdram_device = 0
tCKmin_X_ps = 0
tCKmin_X_minus_1_ps = 0
tCKmin_X_minus_2_ps = 0
tCKmax_ps = 0
caslat_X = 0
tAA_ps = 0
caslat_X_minus_1 = 0
caslat_X_minus_2 = 0
caslat_lowest_derated = 0
tRCD_ps = 0
tRP_ps = 0
tRAS_ps = 0
tWR_ps = 0
tWTR_ps = 0
tRFC_ps = 0
tRRD_ps = 0
tRC_ps = 0
refresh_rate_ps = 0
tIS_ps = 0
tIH_ps = 0
tDS_ps = 0
tDH_ps = 0
tRTP_ps = 0
tDQSQ_max_ps = 0
tQHS_ps = 0



"lowest common" DIMM parameters:  Controller=0
tCKmin_X_ps = 0 (4294967295 MHz)
tCKmax_ps = 0 (4294967295 MHz)
all_DIMMs_burst_lengths_bitmask = 00
tCKmax_max_ps = 0
tRCD_ps = 0
tRP_ps = 0
tRAS_ps = 0
tWR_ps = 0
tWTR_ps = 0
tRFC_ps = 0
tRRD_ps = 0
tRC_ps = 0
refresh_rate_ps = 0
tIS_ps = 0
tDS_ps = 0
tDH_ps = 0
tRTP_ps = 0
tDQSQ_max_ps = 0
tQHS_ps = 0
lowest_common_SPD_caslat = 0
highest_common_derated_caslat = 0
additive_latency = 0
ndimms_present = 1
all_DIMMs_registered = 0
all_DIMMs_unbuffered = 1
all_DIMMs_ECC_capable = 0
total_mem = 2147483648 (2048 megabytes)
base_address = 0 (0 megabytes)


User Config Options: Controller=0
cs0_odt_rd_cfg = 0
cs0_odt_wr_cfg = 1
cs1_odt_rd_cfg = 0
cs1_odt_wr_cfg = 1
cs0_odt_rtt_norm = 3
cs0_odt_rtt_wr = 0
cs1_odt_rtt_norm = 0
cs1_odt_rtt_wr = 0
memctl_interleaving = 0
memctl_interleaving_mode = 0
ba_intlv_ctl = 0x00000040
ECC_mode = 0
ECC_init_using_memctl = 1
DQS_config = 1
self_refresh_in_sleep = 1
dynamic_power = 0
data_bus_width = 0
burst_length = 6
cas_latency_override = 0
cas_latency_override_value = 3
use_derated_caslat = 0
additive_latency_override = 0
additive_latency_override_value = 3
clk_adjust = 6
cpo_override = 31
write_data_delay = 4
half_strength_driver_enable = 0
twoT_en = 0
threeT_en = 0
registered_dimm_en = 0
ap_en = 1
bstopre = 256
wrlvl_override = 1
wrlvl_sample = 10
wrlvl_start = 8
rcw_override = 0
rcw_1 = 0
rcw_2 = 0
tCKE_clock_pulse_width_ps = 9000
tFAW_window_four_activates_ps = 0
trwt_override = 0
trwt = 0


Address Assignment: Controller=0 DIMM=0
Don't have this functionality yet


Computed Register Values: Controller=0
cs0_bnds = 0x0000007F
cs0_config = 0x80014400
cs0_config_2 = 0x00000000
cs1_bnds = 0x00000000
cs1_config = 0x80014400
cs1_config_2 = 0x00000000
timing_cfg_3 = 0x000F0000
timing_cfg_0 = 0x40110104
timing_cfg_1 = 0x000F8246
timing_cfg_2 = 0x0FA8D0C0
ddr_sdram_cfg = 0xC7004000
ddr_sdram_cfg_2 = 0x24401040
ddr_sdram_mode = 0x00401021
ddr_sdram_mode_2 = 0x00000000
ddr_sdram_mode_3 = 0x00000000
ddr_sdram_mode_4 = 0x00000000
ddr_sdram_mode_5 = 0x00000000
ddr_sdram_mode_6 = 0x00000000
ddr_sdram_mode_7 = 0x00000000
ddr_sdram_mode_8 = 0x00000000
ddr_sdram_interval = 0x00000100
ddr_data_init = 0xDEADBEEF
ddr_sdram_clk_cntl = 0x03000000
ddr_init_addr = 0x00000000
ddr_init_ext_addr = 0x00000000
timing_cfg_4 = 0x00220001
timing_cfg_5 = 0x1C401400
ddr_zq_cntl = 0x89080600
ddr_wrlvl_cntl = 0x8675A608
ddr_sr_cntr = 0x00000000
ddr_sdram_rcw_1 = 0x00000000
ddr_sdram_rcw_2 = 0x00000000
ddr_cdr1 = 0x00000000
ddr_cdr2 = 0x00000000
err_disable = 0x00000000
err_int_en = 0x00000000
debug_01 = 0x00000000
debug_02 = 0x00000000
debug_03 = 0x00000000
debug_04 = 0x00000000
debug_05 = 0x00000000
debug_06 = 0x00000000
debug_07 = 0x00000000
debug_08 = 0x00000000
debug_09 = 0x00000000
debug_10 = 0x00000000
debug_11 = 0x00000000
debug_12 = 0x00000000
debug_13 = 0x00000000
debug_14 = 0x00000000
debug_15 = 0x00000000
debug_16 = 0x00000000
debug_17 = 0x00000000
debug_18 = 0x00000000
debug_19 = 0x00000000
debug_20 = 0x00000000
debug_21 = 0x00000000
debug_22 = 0x00000000
debug_23 = 0x00000000
debug_24 = 0x00000000
debug_25 = 0x00000000
debug_26 = 0x00000000
debug_27 = 0x00000000
debug_28 = 0x00000000
debug_29 = 0x00000000
debug_30 = 0x00000000
debug_31 = 0x00000000
debug_32 = 0x00000000

Adding York who might be able to help more...

-M

On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> On Fri, Nov 11, 2011 at 09:07:23PM +0000, McClintock Matthew-B29882 wrote:
>> On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
>> > Thanks. That config_sram.dat is exactly what I came up with.
>> >
>> > I have my board booting via L2SRAM, but the DDR doesn't get configured
>> > correctly yet. I'm trying to figure out how the DDR SPD stuff works in
>> > U-Boot. I've never used it before. I'm following the P2020DS code as an
>> > example, but I haven't yet figured out how the code in
>> > board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
>> > structure especially).
>>
>> If you board has i2c to the ddr modules it should be able to use the
>> timing info from there. I think CONFIG_DDR_SPD is the config option
>> you are looking for. I know the P2020DS does SPD from L2SRAM.
>>
>
> The only thing that looks like an SPD chip is at i2c bus 1, address
> 0x53. I setup my board configuration with:
>
> #define CONFIG_FSL_DDR3
> #define CONFIG_FSL_DDR_INTERACTIVE
> #define CONFIG_CHIP_SELECTS_PER_CTRL    2
> #define CONFIG_SYS_DDR_SBE              0x00010000
>
> #define CONFIG_DDR_SPD
> #define CONFIG_SYS_SPD_BUS_NUM          1
> #define SPD_EEPROM_ADDRESS              0x53
>
> Some of the settings the SPD code computes are correct, and some are
> completely wrong. I can't figure out how to make this work.
>
> Here is the raw SPD dumped from a working U-Boot:
>
> 0000: 92 10 0b 08 02 11 00 09 0b 52 01 08 0c 00 3e 00    .........R....>.
> 0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 05    ixi0i. .p.<<....
> 0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 1f 00    ................
> 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 0070: 00 00 00 00 00 01 94 01 10 25 03 ae 48 48 e3 e3    .........%..HH..
> 0080: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32    SG572568EMR069S2
> 0090: 53 46 00 00 80 ce 53 4d 41 52 54 4d 6f 64 75 6c    SF....SMARTModul
> 00a0: 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    arTechnologies..
> 00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> 00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
>
> And here is the output of an interactive FSL DDR run:
>
> U-Boot 2011.09-00929-g3b5f71c-dirty (Nov 11 2011 - 13:31:13)
>
> CPU0:  P2020E, Version: 2.0, (0x80ea0020)
> Core:  E500, Version: 5.0, (0x80211050)
> Clock Configuration:
>       CPU0:1200 MHz, CPU1:1200 MHz,
>       CCB:600  MHz,
>       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
> L1:    D-cache 32 kB enabled
>       I-cache 32 kB enabled
> Board: Freescale COM Express P2020
> I2C:   ready
> SPI:   ready
> DRAM:  FSL DDR>
> FSL DDR>
> FSL DDR>compute
> unknown module_type 0x08
> Detected UDIMM SG572568EMR069S2SF
> The choosen cas latency 16 is too large
> FSL DDR>print c0 d0
> SPD info:  Controller=0 DIMM=0
> 0      : 92 info_size_crc  bytes written into serial memory, CRC coverage
> 1      : 10 spd_rev        SPD Revision
> 2      : 0b mem_type       Key Byte / DRAM Device Type
> 3      : 08 module_type    Key Byte / Module Type
> 4      : 02 density_banks  SDRAM Density and Banks
> 5      : 11 addressing     SDRAM Addressing
> 6      : 00 module_vdd     Module Nominal Voltage, VDD
> 7      : 09 organization   Module Organization
> 8      : 0b bus_width      Module Memory Bus Width
> 9      : 52 ftb_div        Fine Timebase (FTB) Dividend / Divisor
> 10     : 01 mtb_dividend   Medium Timebase (MTB) Dividend
> 11     : 08 mtb_divisor    Medium Timebase (MTB) Divisor
> 12     : 0c tCK_min        SDRAM Minimum Cycle Time
> 13     : 00 res_13         Reserved
> 14     : 3e caslat_lsb     CAS Latencies Supported, LSB
> 15     : 00 caslat_msb     CAS Latencies Supported, MSB
> 16     : 69 tAA_min        Min CAS Latency Time
> 17     : 78 tWR_min        Min Write REcovery Time
> 18     : 69 tRCD_min       Min RAS# to CAS# Delay Time
> 19     : 30 tRRD_min       Min Row Active to Row Active Delay Time
> 20     : 69 tRP_min        Min Row Precharge Delay Time
> 21     : 11 tRAS_tRC_ext   Upper Nibbles for tRAS and tRC
> 22     : 20 tRAS_min_lsb   Min Active to Precharge Delay Time, LSB
> 23     : 89 tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB
> 24     : 70 tRFC_min_lsb   Min Refresh Recovery Delay Time LSB
> 25     : 03 tRFC_min_msb   Min Refresh Recovery Delay Time MSB
> 26     : 3c tWTR_min       Min Internal Write to Read Command Delay Time
> 27     : 3c tRTP_min Min Internal Read to Precharge Command Delay Time
> 28     : 00 tFAW_msb       Upper Nibble for tFAW
> 29     : f0 tFAW_min       Min Four Activate Window Delay Time
> 30     : 83 opt_features   SDRAM Optional Features
> 31     : 05 therm_ref_opt  SDRAM Thermal and Refresh Opts
> 32     : 80 therm_sensor  SDRAM Thermal Sensor
> 33     : 00 device_type  SDRAM Device Type
> 34 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60 -116: 0f111f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000117    : 01 Module MfgID Code LSB - JEP-106
> 118    : 94 Module MfgID Code MSB - JEP-106
> 119    : 01 Mfg Location
> 120-121: 10 25 Mfg Date
> 122-125: 03 ae 48 48    Module Serial Number
> 126-127: e3 e3   SPD CRC
> 128-145: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 53 46    Mfg's Module Part Number
> 146-147: 00 00 Module Revision code
> 148    : 80 DRAM MfgID Code LSB - JEP-106
> 149    : ce DRAM MfgID Code MSB - JEP-106
> 150-175: 53 4d 41 52 54 4d 6f 64 75 6c 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    Mfg's Specific Data
> 176-255: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000   Mfg's Specific Data
>
>
>
> DIMM parameters:  Controller=0 DIMM=0
> DIMM organization parameters:
> module part name = SG572568EMR069S2SF
> rank_density = 1073741824 bytes (1024 megabytes)
> capacity = 2147483648 bytes (2048 megabytes)
> burst_lengths_bitmask = 00
> base_addresss = 0 (00000000 00000000)
> n_ranks = 2
> data_width = 72
> primary_sdram_width = 64
> ec_sdram_width = 8
> registered_dimm = 0
> n_row_addr = 0
> n_col_addr = 0
> edc_config = 0
> n_banks_per_sdram_device = 0
> tCKmin_X_ps = 0
> tCKmin_X_minus_1_ps = 0
> tCKmin_X_minus_2_ps = 0
> tCKmax_ps = 0
> caslat_X = 0
> tAA_ps = 0
> caslat_X_minus_1 = 0
> caslat_X_minus_2 = 0
> caslat_lowest_derated = 0
> tRCD_ps = 0
> tRP_ps = 0
> tRAS_ps = 0
> tWR_ps = 0
> tWTR_ps = 0
> tRFC_ps = 0
> tRRD_ps = 0
> tRC_ps = 0
> refresh_rate_ps = 0
> tIS_ps = 0
> tIH_ps = 0
> tDS_ps = 0
> tDH_ps = 0
> tRTP_ps = 0
> tDQSQ_max_ps = 0
> tQHS_ps = 0
>
>
>
> "lowest common" DIMM parameters:  Controller=0
> tCKmin_X_ps = 0 (4294967295 MHz)
> tCKmax_ps = 0 (4294967295 MHz)
> all_DIMMs_burst_lengths_bitmask = 00
> tCKmax_max_ps = 0
> tRCD_ps = 0
> tRP_ps = 0
> tRAS_ps = 0
> tWR_ps = 0
> tWTR_ps = 0
> tRFC_ps = 0
> tRRD_ps = 0
> tRC_ps = 0
> refresh_rate_ps = 0
> tIS_ps = 0
> tDS_ps = 0
> tDH_ps = 0
> tRTP_ps = 0
> tDQSQ_max_ps = 0
> tQHS_ps = 0
> lowest_common_SPD_caslat = 0
> highest_common_derated_caslat = 0
> additive_latency = 0
> ndimms_present = 1
> all_DIMMs_registered = 0
> all_DIMMs_unbuffered = 1
> all_DIMMs_ECC_capable = 0
> total_mem = 2147483648 (2048 megabytes)
> base_address = 0 (0 megabytes)
>
>
> User Config Options: Controller=0
> cs0_odt_rd_cfg = 0
> cs0_odt_wr_cfg = 1
> cs1_odt_rd_cfg = 0
> cs1_odt_wr_cfg = 1
> cs0_odt_rtt_norm = 3
> cs0_odt_rtt_wr = 0
> cs1_odt_rtt_norm = 0
> cs1_odt_rtt_wr = 0
> memctl_interleaving = 0
> memctl_interleaving_mode = 0
> ba_intlv_ctl = 0x00000040
> ECC_mode = 0
> ECC_init_using_memctl = 1
> DQS_config = 1
> self_refresh_in_sleep = 1
> dynamic_power = 0
> data_bus_width = 0
> burst_length = 6
> cas_latency_override = 0
> cas_latency_override_value = 3
> use_derated_caslat = 0
> additive_latency_override = 0
> additive_latency_override_value = 3
> clk_adjust = 6
> cpo_override = 31
> write_data_delay = 4
> half_strength_driver_enable = 0
> twoT_en = 0
> threeT_en = 0
> registered_dimm_en = 0
> ap_en = 1
> bstopre = 256
> wrlvl_override = 1
> wrlvl_sample = 10
> wrlvl_start = 8
> rcw_override = 0
> rcw_1 = 0
> rcw_2 = 0
> tCKE_clock_pulse_width_ps = 9000
> tFAW_window_four_activates_ps = 0
> trwt_override = 0
> trwt = 0
>
>
> Address Assignment: Controller=0 DIMM=0
> Don't have this functionality yet
>
>
> Computed Register Values: Controller=0
> cs0_bnds = 0x0000007F
> cs0_config = 0x80014400
> cs0_config_2 = 0x00000000
> cs1_bnds = 0x00000000
> cs1_config = 0x80014400
> cs1_config_2 = 0x00000000
> timing_cfg_3 = 0x000F0000
> timing_cfg_0 = 0x40110104
> timing_cfg_1 = 0x000F8246
> timing_cfg_2 = 0x0FA8D0C0
> ddr_sdram_cfg = 0xC7004000
> ddr_sdram_cfg_2 = 0x24401040
> ddr_sdram_mode = 0x00401021
> ddr_sdram_mode_2 = 0x00000000
> ddr_sdram_mode_3 = 0x00000000
> ddr_sdram_mode_4 = 0x00000000
> ddr_sdram_mode_5 = 0x00000000
> ddr_sdram_mode_6 = 0x00000000
> ddr_sdram_mode_7 = 0x00000000
> ddr_sdram_mode_8 = 0x00000000
> ddr_sdram_interval = 0x00000100
> ddr_data_init = 0xDEADBEEF
> ddr_sdram_clk_cntl = 0x03000000
> ddr_init_addr = 0x00000000
> ddr_init_ext_addr = 0x00000000
> timing_cfg_4 = 0x00220001
> timing_cfg_5 = 0x1C401400
> ddr_zq_cntl = 0x89080600
> ddr_wrlvl_cntl = 0x8675A608
> ddr_sr_cntr = 0x00000000
> ddr_sdram_rcw_1 = 0x00000000
> ddr_sdram_rcw_2 = 0x00000000
> ddr_cdr1 = 0x00000000
> ddr_cdr2 = 0x00000000
> err_disable = 0x00000000
> err_int_en = 0x00000000
> debug_01 = 0x00000000
> debug_02 = 0x00000000
> debug_03 = 0x00000000
> debug_04 = 0x00000000
> debug_05 = 0x00000000
> debug_06 = 0x00000000
> debug_07 = 0x00000000
> debug_08 = 0x00000000
> debug_09 = 0x00000000
> debug_10 = 0x00000000
> debug_11 = 0x00000000
> debug_12 = 0x00000000
> debug_13 = 0x00000000
> debug_14 = 0x00000000
> debug_15 = 0x00000000
> debug_16 = 0x00000000
> debug_17 = 0x00000000
> debug_18 = 0x00000000
> debug_19 = 0x00000000
> debug_20 = 0x00000000
> debug_21 = 0x00000000
> debug_22 = 0x00000000
> debug_23 = 0x00000000
> debug_24 = 0x00000000
> debug_25 = 0x00000000
> debug_26 = 0x00000000
> debug_27 = 0x00000000
> debug_28 = 0x00000000
> debug_29 = 0x00000000
> debug_30 = 0x00000000
> debug_31 = 0x00000000
> debug_32 = 0x00000000
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

Looking good so far, what's the question? You can always override the
register values and try it since you got the interactive debug up.

York



On Fri, 2011-11-11 at 14:54 -0800, McClintock Matthew-B29882 wrote:
> Adding York who might be able to help more...
> 
> -M
> 
> On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > On Fri, Nov 11, 2011 at 09:07:23PM +0000, McClintock Matthew-B29882 wrote:
> >> On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> >> > Thanks. That config_sram.dat is exactly what I came up with.
> >> >
> >> > I have my board booting via L2SRAM, but the DDR doesn't get configured
> >> > correctly yet. I'm trying to figure out how the DDR SPD stuff works in
> >> > U-Boot. I've never used it before. I'm following the P2020DS code as an
> >> > example, but I haven't yet figured out how the code in
> >> > board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
> >> > structure especially).
> >>
> >> If you board has i2c to the ddr modules it should be able to use the
> >> timing info from there. I think CONFIG_DDR_SPD is the config option
> >> you are looking for. I know the P2020DS does SPD from L2SRAM.
> >>
> >
> > The only thing that looks like an SPD chip is at i2c bus 1, address
> > 0x53. I setup my board configuration with:
> >
> > #define CONFIG_FSL_DDR3
> > #define CONFIG_FSL_DDR_INTERACTIVE
> > #define CONFIG_CHIP_SELECTS_PER_CTRL    2
> > #define CONFIG_SYS_DDR_SBE              0x00010000
> >
> > #define CONFIG_DDR_SPD
> > #define CONFIG_SYS_SPD_BUS_NUM          1
> > #define SPD_EEPROM_ADDRESS              0x53
> >
> > Some of the settings the SPD code computes are correct, and some are
> > completely wrong. I can't figure out how to make this work.
> >
> > Here is the raw SPD dumped from a working U-Boot:
> >
> > 0000: 92 10 0b 08 02 11 00 09 0b 52 01 08 0c 00 3e 00    .........R....>.
> > 0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 05    ixi0i. .p.<<....
> > 0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 1f 00    ................
> > 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 0070: 00 00 00 00 00 01 94 01 10 25 03 ae 48 48 e3 e3    .........%..HH..
> > 0080: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32    SG572568EMR069S2
> > 0090: 53 46 00 00 80 ce 53 4d 41 52 54 4d 6f 64 75 6c    SF....SMARTModul
> > 00a0: 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    arTechnologies..
> > 00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > 00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> >
> > And here is the output of an interactive FSL DDR run:
> >
> > U-Boot 2011.09-00929-g3b5f71c-dirty (Nov 11 2011 - 13:31:13)
> >
> > CPU0:  P2020E, Version: 2.0, (0x80ea0020)
> > Core:  E500, Version: 5.0, (0x80211050)
> > Clock Configuration:
> >       CPU0:1200 MHz, CPU1:1200 MHz,
> >       CCB:600  MHz,
> >       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
> > L1:    D-cache 32 kB enabled
> >       I-cache 32 kB enabled
> > Board: Freescale COM Express P2020
> > I2C:   ready
> > SPI:   ready
> > DRAM:  FSL DDR>
> > FSL DDR>
> > FSL DDR>compute
> > unknown module_type 0x08
> > Detected UDIMM SG572568EMR069S2SF
> > The choosen cas latency 16 is too large
> > FSL DDR>print c0 d0
> > SPD info:  Controller=0 DIMM=0
> > 0      : 92 info_size_crc  bytes written into serial memory, CRC coverage
> > 1      : 10 spd_rev        SPD Revision
> > 2      : 0b mem_type       Key Byte / DRAM Device Type
> > 3      : 08 module_type    Key Byte / Module Type
> > 4      : 02 density_banks  SDRAM Density and Banks
> > 5      : 11 addressing     SDRAM Addressing
> > 6      : 00 module_vdd     Module Nominal Voltage, VDD
> > 7      : 09 organization   Module Organization
> > 8      : 0b bus_width      Module Memory Bus Width
> > 9      : 52 ftb_div        Fine Timebase (FTB) Dividend / Divisor
> > 10     : 01 mtb_dividend   Medium Timebase (MTB) Dividend
> > 11     : 08 mtb_divisor    Medium Timebase (MTB) Divisor
> > 12     : 0c tCK_min        SDRAM Minimum Cycle Time
> > 13     : 00 res_13         Reserved
> > 14     : 3e caslat_lsb     CAS Latencies Supported, LSB
> > 15     : 00 caslat_msb     CAS Latencies Supported, MSB
> > 16     : 69 tAA_min        Min CAS Latency Time
> > 17     : 78 tWR_min        Min Write REcovery Time
> > 18     : 69 tRCD_min       Min RAS# to CAS# Delay Time
> > 19     : 30 tRRD_min       Min Row Active to Row Active Delay Time
> > 20     : 69 tRP_min        Min Row Precharge Delay Time
> > 21     : 11 tRAS_tRC_ext   Upper Nibbles for tRAS and tRC
> > 22     : 20 tRAS_min_lsb   Min Active to Precharge Delay Time, LSB
> > 23     : 89 tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB
> > 24     : 70 tRFC_min_lsb   Min Refresh Recovery Delay Time LSB
> > 25     : 03 tRFC_min_msb   Min Refresh Recovery Delay Time MSB
> > 26     : 3c tWTR_min       Min Internal Write to Read Command Delay Time
> > 27     : 3c tRTP_min Min Internal Read to Precharge Command Delay Time
> > 28     : 00 tFAW_msb       Upper Nibble for tFAW
> > 29     : f0 tFAW_min       Min Four Activate Window Delay Time
> > 30     : 83 opt_features   SDRAM Optional Features
> > 31     : 05 therm_ref_opt  SDRAM Thermal and Refresh Opts
> > 32     : 80 therm_sensor  SDRAM Thermal Sensor
> > 33     : 00 device_type  SDRAM Device Type
> > 34 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 60 -116: 0f111f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000117    : 01 Module MfgID Code LSB - JEP-106
> > 118    : 94 Module MfgID Code MSB - JEP-106
> > 119    : 01 Mfg Location
> > 120-121: 10 25 Mfg Date
> > 122-125: 03 ae 48 48    Module Serial Number
> > 126-127: e3 e3   SPD CRC
> > 128-145: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 53 46    Mfg's Module Part Number
> > 146-147: 00 00 Module Revision code
> > 148    : 80 DRAM MfgID Code LSB - JEP-106
> > 149    : ce DRAM MfgID Code MSB - JEP-106
> > 150-175: 53 4d 41 52 54 4d 6f 64 75 6c 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    Mfg's Specific Data
> > 176-255: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000   Mfg's Specific Data
> >
> >
> >
> > DIMM parameters:  Controller=0 DIMM=0
> > DIMM organization parameters:
> > module part name = SG572568EMR069S2SF
> > rank_density = 1073741824 bytes (1024 megabytes)
> > capacity = 2147483648 bytes (2048 megabytes)
> > burst_lengths_bitmask = 00
> > base_addresss = 0 (00000000 00000000)
> > n_ranks = 2
> > data_width = 72
> > primary_sdram_width = 64
> > ec_sdram_width = 8
> > registered_dimm = 0
> > n_row_addr = 0
> > n_col_addr = 0
> > edc_config = 0
> > n_banks_per_sdram_device = 0
> > tCKmin_X_ps = 0
> > tCKmin_X_minus_1_ps = 0
> > tCKmin_X_minus_2_ps = 0
> > tCKmax_ps = 0
> > caslat_X = 0
> > tAA_ps = 0
> > caslat_X_minus_1 = 0
> > caslat_X_minus_2 = 0
> > caslat_lowest_derated = 0
> > tRCD_ps = 0
> > tRP_ps = 0
> > tRAS_ps = 0
> > tWR_ps = 0
> > tWTR_ps = 0
> > tRFC_ps = 0
> > tRRD_ps = 0
> > tRC_ps = 0
> > refresh_rate_ps = 0
> > tIS_ps = 0
> > tIH_ps = 0
> > tDS_ps = 0
> > tDH_ps = 0
> > tRTP_ps = 0
> > tDQSQ_max_ps = 0
> > tQHS_ps = 0
> >
> >
> >
> > "lowest common" DIMM parameters:  Controller=0
> > tCKmin_X_ps = 0 (4294967295 MHz)
> > tCKmax_ps = 0 (4294967295 MHz)
> > all_DIMMs_burst_lengths_bitmask = 00
> > tCKmax_max_ps = 0
> > tRCD_ps = 0
> > tRP_ps = 0
> > tRAS_ps = 0
> > tWR_ps = 0
> > tWTR_ps = 0
> > tRFC_ps = 0
> > tRRD_ps = 0
> > tRC_ps = 0
> > refresh_rate_ps = 0
> > tIS_ps = 0
> > tDS_ps = 0
> > tDH_ps = 0
> > tRTP_ps = 0
> > tDQSQ_max_ps = 0
> > tQHS_ps = 0
> > lowest_common_SPD_caslat = 0
> > highest_common_derated_caslat = 0
> > additive_latency = 0
> > ndimms_present = 1
> > all_DIMMs_registered = 0
> > all_DIMMs_unbuffered = 1
> > all_DIMMs_ECC_capable = 0
> > total_mem = 2147483648 (2048 megabytes)
> > base_address = 0 (0 megabytes)
> >
> >
> > User Config Options: Controller=0
> > cs0_odt_rd_cfg = 0
> > cs0_odt_wr_cfg = 1
> > cs1_odt_rd_cfg = 0
> > cs1_odt_wr_cfg = 1
> > cs0_odt_rtt_norm = 3
> > cs0_odt_rtt_wr = 0
> > cs1_odt_rtt_norm = 0
> > cs1_odt_rtt_wr = 0
> > memctl_interleaving = 0
> > memctl_interleaving_mode = 0
> > ba_intlv_ctl = 0x00000040
> > ECC_mode = 0
> > ECC_init_using_memctl = 1
> > DQS_config = 1
> > self_refresh_in_sleep = 1
> > dynamic_power = 0
> > data_bus_width = 0
> > burst_length = 6
> > cas_latency_override = 0
> > cas_latency_override_value = 3
> > use_derated_caslat = 0
> > additive_latency_override = 0
> > additive_latency_override_value = 3
> > clk_adjust = 6
> > cpo_override = 31
> > write_data_delay = 4
> > half_strength_driver_enable = 0
> > twoT_en = 0
> > threeT_en = 0
> > registered_dimm_en = 0
> > ap_en = 1
> > bstopre = 256
> > wrlvl_override = 1
> > wrlvl_sample = 10
> > wrlvl_start = 8
> > rcw_override = 0
> > rcw_1 = 0
> > rcw_2 = 0
> > tCKE_clock_pulse_width_ps = 9000
> > tFAW_window_four_activates_ps = 0
> > trwt_override = 0
> > trwt = 0
> >
> >
> > Address Assignment: Controller=0 DIMM=0
> > Don't have this functionality yet
> >
> >
> > Computed Register Values: Controller=0
> > cs0_bnds = 0x0000007F
> > cs0_config = 0x80014400
> > cs0_config_2 = 0x00000000
> > cs1_bnds = 0x00000000
> > cs1_config = 0x80014400
> > cs1_config_2 = 0x00000000
> > timing_cfg_3 = 0x000F0000
> > timing_cfg_0 = 0x40110104
> > timing_cfg_1 = 0x000F8246
> > timing_cfg_2 = 0x0FA8D0C0
> > ddr_sdram_cfg = 0xC7004000
> > ddr_sdram_cfg_2 = 0x24401040
> > ddr_sdram_mode = 0x00401021
> > ddr_sdram_mode_2 = 0x00000000
> > ddr_sdram_mode_3 = 0x00000000
> > ddr_sdram_mode_4 = 0x00000000
> > ddr_sdram_mode_5 = 0x00000000
> > ddr_sdram_mode_6 = 0x00000000
> > ddr_sdram_mode_7 = 0x00000000
> > ddr_sdram_mode_8 = 0x00000000
> > ddr_sdram_interval = 0x00000100
> > ddr_data_init = 0xDEADBEEF
> > ddr_sdram_clk_cntl = 0x03000000
> > ddr_init_addr = 0x00000000
> > ddr_init_ext_addr = 0x00000000
> > timing_cfg_4 = 0x00220001
> > timing_cfg_5 = 0x1C401400
> > ddr_zq_cntl = 0x89080600
> > ddr_wrlvl_cntl = 0x8675A608
> > ddr_sr_cntr = 0x00000000
> > ddr_sdram_rcw_1 = 0x00000000
> > ddr_sdram_rcw_2 = 0x00000000
> > ddr_cdr1 = 0x00000000
> > ddr_cdr2 = 0x00000000
> > err_disable = 0x00000000
> > err_int_en = 0x00000000
> > debug_01 = 0x00000000
> > debug_02 = 0x00000000
> > debug_03 = 0x00000000
> > debug_04 = 0x00000000
> > debug_05 = 0x00000000
> > debug_06 = 0x00000000
> > debug_07 = 0x00000000
> > debug_08 = 0x00000000
> > debug_09 = 0x00000000
> > debug_10 = 0x00000000
> > debug_11 = 0x00000000
> > debug_12 = 0x00000000
> > debug_13 = 0x00000000
> > debug_14 = 0x00000000
> > debug_15 = 0x00000000
> > debug_16 = 0x00000000
> > debug_17 = 0x00000000
> > debug_18 = 0x00000000
> > debug_19 = 0x00000000
> > debug_20 = 0x00000000
> > debug_21 = 0x00000000
> > debug_22 = 0x00000000
> > debug_23 = 0x00000000
> > debug_24 = 0x00000000
> > debug_25 = 0x00000000
> > debug_26 = 0x00000000
> > debug_27 = 0x00000000
> > debug_28 = 0x00000000
> > debug_29 = 0x00000000
> > debug_30 = 0x00000000
> > debug_31 = 0x00000000
> > debug_32 = 0x00000000
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >

On Fri, Nov 11, 2011 at 03:02:46PM -0800, York Sun wrote:
> Looking good so far, what's the question? You can always override the
> register values and try it since you got the interactive debug up.
> 

Well, it doesn't work out of the box.

I'm very worried about the following messages:
> unknown module_type 0x08
> Detected UDIMM SG572568EMR069S2SF
> The choosen cas latency 16 is too large

I copied the settings from the configuration for the On-Chip ROM's RAM
setup. I issued the following in the interactive DDR setup:

FSL-DDR> compute
FSL-DDR> edit c0 d0 regs ddr_sdram_cfg e7000008
... lots more ...
FSL-DDR> go

That didn't work. Maybe I did something wrong? I'll try again.

Ira

> York
> 
> 
> 
> On Fri, 2011-11-11 at 14:54 -0800, McClintock Matthew-B29882 wrote:
> > Adding York who might be able to help more...
> > 
> > -M
> > 
> > On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > > On Fri, Nov 11, 2011 at 09:07:23PM +0000, McClintock Matthew-B29882 wrote:
> > >> On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > >> > Thanks. That config_sram.dat is exactly what I came up with.
> > >> >
> > >> > I have my board booting via L2SRAM, but the DDR doesn't get configured
> > >> > correctly yet. I'm trying to figure out how the DDR SPD stuff works in
> > >> > U-Boot. I've never used it before. I'm following the P2020DS code as an
> > >> > example, but I haven't yet figured out how the code in
> > >> > board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
> > >> > structure especially).
> > >>
> > >> If you board has i2c to the ddr modules it should be able to use the
> > >> timing info from there. I think CONFIG_DDR_SPD is the config option
> > >> you are looking for. I know the P2020DS does SPD from L2SRAM.
> > >>
> > >
> > > The only thing that looks like an SPD chip is at i2c bus 1, address
> > > 0x53. I setup my board configuration with:
> > >
> > > #define CONFIG_FSL_DDR3
> > > #define CONFIG_FSL_DDR_INTERACTIVE
> > > #define CONFIG_CHIP_SELECTS_PER_CTRL    2
> > > #define CONFIG_SYS_DDR_SBE              0x00010000
> > >
> > > #define CONFIG_DDR_SPD
> > > #define CONFIG_SYS_SPD_BUS_NUM          1
> > > #define SPD_EEPROM_ADDRESS              0x53
> > >
> > > Some of the settings the SPD code computes are correct, and some are
> > > completely wrong. I can't figure out how to make this work.
> > >
> > > Here is the raw SPD dumped from a working U-Boot:
> > >
> > > 0000: 92 10 0b 08 02 11 00 09 0b 52 01 08 0c 00 3e 00    .........R....>.
> > > 0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 05    ixi0i. .p.<<....
> > > 0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 1f 00    ................
> > > 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 0070: 00 00 00 00 00 01 94 01 10 25 03 ae 48 48 e3 e3    .........%..HH..
> > > 0080: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32    SG572568EMR069S2
> > > 0090: 53 46 00 00 80 ce 53 4d 41 52 54 4d 6f 64 75 6c    SF....SMARTModul
> > > 00a0: 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    arTechnologies..
> > > 00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > 00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > >
> > > And here is the output of an interactive FSL DDR run:
> > >
> > > U-Boot 2011.09-00929-g3b5f71c-dirty (Nov 11 2011 - 13:31:13)
> > >
> > > CPU0:  P2020E, Version: 2.0, (0x80ea0020)
> > > Core:  E500, Version: 5.0, (0x80211050)
> > > Clock Configuration:
> > >       CPU0:1200 MHz, CPU1:1200 MHz,
> > >       CCB:600  MHz,
> > >       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
> > > L1:    D-cache 32 kB enabled
> > >       I-cache 32 kB enabled
> > > Board: Freescale COM Express P2020
> > > I2C:   ready
> > > SPI:   ready
> > > DRAM:  FSL DDR>
> > > FSL DDR>
> > > FSL DDR>compute
> > > unknown module_type 0x08
> > > Detected UDIMM SG572568EMR069S2SF
> > > The choosen cas latency 16 is too large
> > > FSL DDR>print c0 d0
> > > SPD info:  Controller=0 DIMM=0
> > > 0      : 92 info_size_crc  bytes written into serial memory, CRC coverage
> > > 1      : 10 spd_rev        SPD Revision
> > > 2      : 0b mem_type       Key Byte / DRAM Device Type
> > > 3      : 08 module_type    Key Byte / Module Type
> > > 4      : 02 density_banks  SDRAM Density and Banks
> > > 5      : 11 addressing     SDRAM Addressing
> > > 6      : 00 module_vdd     Module Nominal Voltage, VDD
> > > 7      : 09 organization   Module Organization
> > > 8      : 0b bus_width      Module Memory Bus Width
> > > 9      : 52 ftb_div        Fine Timebase (FTB) Dividend / Divisor
> > > 10     : 01 mtb_dividend   Medium Timebase (MTB) Dividend
> > > 11     : 08 mtb_divisor    Medium Timebase (MTB) Divisor
> > > 12     : 0c tCK_min        SDRAM Minimum Cycle Time
> > > 13     : 00 res_13         Reserved
> > > 14     : 3e caslat_lsb     CAS Latencies Supported, LSB
> > > 15     : 00 caslat_msb     CAS Latencies Supported, MSB
> > > 16     : 69 tAA_min        Min CAS Latency Time
> > > 17     : 78 tWR_min        Min Write REcovery Time
> > > 18     : 69 tRCD_min       Min RAS# to CAS# Delay Time
> > > 19     : 30 tRRD_min       Min Row Active to Row Active Delay Time
> > > 20     : 69 tRP_min        Min Row Precharge Delay Time
> > > 21     : 11 tRAS_tRC_ext   Upper Nibbles for tRAS and tRC
> > > 22     : 20 tRAS_min_lsb   Min Active to Precharge Delay Time, LSB
> > > 23     : 89 tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB
> > > 24     : 70 tRFC_min_lsb   Min Refresh Recovery Delay Time LSB
> > > 25     : 03 tRFC_min_msb   Min Refresh Recovery Delay Time MSB
> > > 26     : 3c tWTR_min       Min Internal Write to Read Command Delay Time
> > > 27     : 3c tRTP_min Min Internal Read to Precharge Command Delay Time
> > > 28     : 00 tFAW_msb       Upper Nibble for tFAW
> > > 29     : f0 tFAW_min       Min Four Activate Window Delay Time
> > > 30     : 83 opt_features   SDRAM Optional Features
> > > 31     : 05 therm_ref_opt  SDRAM Thermal and Refresh Opts
> > > 32     : 80 therm_sensor  SDRAM Thermal Sensor
> > > 33     : 00 device_type  SDRAM Device Type
> > > 34 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > > 60 -116: 0f111f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000117    : 01 Module MfgID Code LSB - JEP-106
> > > 118    : 94 Module MfgID Code MSB - JEP-106
> > > 119    : 01 Mfg Location
> > > 120-121: 10 25 Mfg Date
> > > 122-125: 03 ae 48 48    Module Serial Number
> > > 126-127: e3 e3   SPD CRC
> > > 128-145: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 53 46    Mfg's Module Part Number
> > > 146-147: 00 00 Module Revision code
> > > 148    : 80 DRAM MfgID Code LSB - JEP-106
> > > 149    : ce DRAM MfgID Code MSB - JEP-106
> > > 150-175: 53 4d 41 52 54 4d 6f 64 75 6c 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    Mfg's Specific Data
> > > 176-255: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000   Mfg's Specific Data
> > >
> > >
> > >
> > > DIMM parameters:  Controller=0 DIMM=0
> > > DIMM organization parameters:
> > > module part name = SG572568EMR069S2SF
> > > rank_density = 1073741824 bytes (1024 megabytes)
> > > capacity = 2147483648 bytes (2048 megabytes)
> > > burst_lengths_bitmask = 00
> > > base_addresss = 0 (00000000 00000000)
> > > n_ranks = 2
> > > data_width = 72
> > > primary_sdram_width = 64
> > > ec_sdram_width = 8
> > > registered_dimm = 0
> > > n_row_addr = 0
> > > n_col_addr = 0
> > > edc_config = 0
> > > n_banks_per_sdram_device = 0
> > > tCKmin_X_ps = 0
> > > tCKmin_X_minus_1_ps = 0
> > > tCKmin_X_minus_2_ps = 0
> > > tCKmax_ps = 0
> > > caslat_X = 0
> > > tAA_ps = 0
> > > caslat_X_minus_1 = 0
> > > caslat_X_minus_2 = 0
> > > caslat_lowest_derated = 0
> > > tRCD_ps = 0
> > > tRP_ps = 0
> > > tRAS_ps = 0
> > > tWR_ps = 0
> > > tWTR_ps = 0
> > > tRFC_ps = 0
> > > tRRD_ps = 0
> > > tRC_ps = 0
> > > refresh_rate_ps = 0
> > > tIS_ps = 0
> > > tIH_ps = 0
> > > tDS_ps = 0
> > > tDH_ps = 0
> > > tRTP_ps = 0
> > > tDQSQ_max_ps = 0
> > > tQHS_ps = 0
> > >
> > >
> > >
> > > "lowest common" DIMM parameters:  Controller=0
> > > tCKmin_X_ps = 0 (4294967295 MHz)
> > > tCKmax_ps = 0 (4294967295 MHz)
> > > all_DIMMs_burst_lengths_bitmask = 00
> > > tCKmax_max_ps = 0
> > > tRCD_ps = 0
> > > tRP_ps = 0
> > > tRAS_ps = 0
> > > tWR_ps = 0
> > > tWTR_ps = 0
> > > tRFC_ps = 0
> > > tRRD_ps = 0
> > > tRC_ps = 0
> > > refresh_rate_ps = 0
> > > tIS_ps = 0
> > > tDS_ps = 0
> > > tDH_ps = 0
> > > tRTP_ps = 0
> > > tDQSQ_max_ps = 0
> > > tQHS_ps = 0
> > > lowest_common_SPD_caslat = 0
> > > highest_common_derated_caslat = 0
> > > additive_latency = 0
> > > ndimms_present = 1
> > > all_DIMMs_registered = 0
> > > all_DIMMs_unbuffered = 1
> > > all_DIMMs_ECC_capable = 0
> > > total_mem = 2147483648 (2048 megabytes)
> > > base_address = 0 (0 megabytes)
> > >
> > >
> > > User Config Options: Controller=0
> > > cs0_odt_rd_cfg = 0
> > > cs0_odt_wr_cfg = 1
> > > cs1_odt_rd_cfg = 0
> > > cs1_odt_wr_cfg = 1
> > > cs0_odt_rtt_norm = 3
> > > cs0_odt_rtt_wr = 0
> > > cs1_odt_rtt_norm = 0
> > > cs1_odt_rtt_wr = 0
> > > memctl_interleaving = 0
> > > memctl_interleaving_mode = 0
> > > ba_intlv_ctl = 0x00000040
> > > ECC_mode = 0
> > > ECC_init_using_memctl = 1
> > > DQS_config = 1
> > > self_refresh_in_sleep = 1
> > > dynamic_power = 0
> > > data_bus_width = 0
> > > burst_length = 6
> > > cas_latency_override = 0
> > > cas_latency_override_value = 3
> > > use_derated_caslat = 0
> > > additive_latency_override = 0
> > > additive_latency_override_value = 3
> > > clk_adjust = 6
> > > cpo_override = 31
> > > write_data_delay = 4
> > > half_strength_driver_enable = 0
> > > twoT_en = 0
> > > threeT_en = 0
> > > registered_dimm_en = 0
> > > ap_en = 1
> > > bstopre = 256
> > > wrlvl_override = 1
> > > wrlvl_sample = 10
> > > wrlvl_start = 8
> > > rcw_override = 0
> > > rcw_1 = 0
> > > rcw_2 = 0
> > > tCKE_clock_pulse_width_ps = 9000
> > > tFAW_window_four_activates_ps = 0
> > > trwt_override = 0
> > > trwt = 0
> > >
> > >
> > > Address Assignment: Controller=0 DIMM=0
> > > Don't have this functionality yet
> > >
> > >
> > > Computed Register Values: Controller=0
> > > cs0_bnds = 0x0000007F
> > > cs0_config = 0x80014400
> > > cs0_config_2 = 0x00000000
> > > cs1_bnds = 0x00000000
> > > cs1_config = 0x80014400
> > > cs1_config_2 = 0x00000000
> > > timing_cfg_3 = 0x000F0000
> > > timing_cfg_0 = 0x40110104
> > > timing_cfg_1 = 0x000F8246
> > > timing_cfg_2 = 0x0FA8D0C0
> > > ddr_sdram_cfg = 0xC7004000
> > > ddr_sdram_cfg_2 = 0x24401040
> > > ddr_sdram_mode = 0x00401021
> > > ddr_sdram_mode_2 = 0x00000000
> > > ddr_sdram_mode_3 = 0x00000000
> > > ddr_sdram_mode_4 = 0x00000000
> > > ddr_sdram_mode_5 = 0x00000000
> > > ddr_sdram_mode_6 = 0x00000000
> > > ddr_sdram_mode_7 = 0x00000000
> > > ddr_sdram_mode_8 = 0x00000000
> > > ddr_sdram_interval = 0x00000100
> > > ddr_data_init = 0xDEADBEEF
> > > ddr_sdram_clk_cntl = 0x03000000
> > > ddr_init_addr = 0x00000000
> > > ddr_init_ext_addr = 0x00000000
> > > timing_cfg_4 = 0x00220001
> > > timing_cfg_5 = 0x1C401400
> > > ddr_zq_cntl = 0x89080600
> > > ddr_wrlvl_cntl = 0x8675A608
> > > ddr_sr_cntr = 0x00000000
> > > ddr_sdram_rcw_1 = 0x00000000
> > > ddr_sdram_rcw_2 = 0x00000000
> > > ddr_cdr1 = 0x00000000
> > > ddr_cdr2 = 0x00000000
> > > err_disable = 0x00000000
> > > err_int_en = 0x00000000
> > > debug_01 = 0x00000000
> > > debug_02 = 0x00000000
> > > debug_03 = 0x00000000
> > > debug_04 = 0x00000000
> > > debug_05 = 0x00000000
> > > debug_06 = 0x00000000
> > > debug_07 = 0x00000000
> > > debug_08 = 0x00000000
> > > debug_09 = 0x00000000
> > > debug_10 = 0x00000000
> > > debug_11 = 0x00000000
> > > debug_12 = 0x00000000
> > > debug_13 = 0x00000000
> > > debug_14 = 0x00000000
> > > debug_15 = 0x00000000
> > > debug_16 = 0x00000000
> > > debug_17 = 0x00000000
> > > debug_18 = 0x00000000
> > > debug_19 = 0x00000000
> > > debug_20 = 0x00000000
> > > debug_21 = 0x00000000
> > > debug_22 = 0x00000000
> > > debug_23 = 0x00000000
> > > debug_24 = 0x00000000
> > > debug_25 = 0x00000000
> > > debug_26 = 0x00000000
> > > debug_27 = 0x00000000
> > > debug_28 = 0x00000000
> > > debug_29 = 0x00000000
> > > debug_30 = 0x00000000
> > > debug_31 = 0x00000000
> > > debug_32 = 0x00000000
> > >
> > > _______________________________________________
> > > U-Boot mailing list
> > > U-Boot@lists.denx.de
> > > http://lists.denx.de/mailman/listinfo/u-boot
> > >
> 
> 
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

On Fri, Nov 11, 2011 at 03:10:43PM -0800, Ira W. Snyder wrote:
> On Fri, Nov 11, 2011 at 03:02:46PM -0800, York Sun wrote:
> > Looking good so far, what's the question? You can always override the
> > register values and try it since you got the interactive debug up.
> > 
> 
> Well, it doesn't work out of the box.
> 
> I'm very worried about the following messages:
> > unknown module_type 0x08
> > Detected UDIMM SG572568EMR069S2SF
> > The choosen cas latency 16 is too large
> 
> I copied the settings from the configuration for the On-Chip ROM's RAM
> setup. I issued the following in the interactive DDR setup:
> 
> FSL-DDR> compute
> FSL-DDR> edit c0 d0 regs ddr_sdram_cfg e7000008
> ... lots more ...
> FSL-DDR> go
> 
> That didn't work. Maybe I did something wrong? I'll try again.

I tried again. It turns out "edit" values have to be prefixed by "0x"
for hex values (unlike the rest of U-Boot).

The commands I used. You can double check that they match the
config_sram_blackadder2020.dat posted earlier in this thread.

edit c0 d0 regs ddr_sdram_cfg		0x67000008
edit c0 d0 regs cs0_bnds		0x0000003f
edit c0 d0 regs cs1_bnds		0x0040007f
edit c0 d0 regs cs0_config		0x80014202
edit c0 d0 regs cs1_config		0x80014202
edit c0 d0 regs timing_cfg_0		0x00330804
edit c0 d0 regs timing_cfg_1		0x6f6b4644
edit c0 d0 regs timing_cfg_2		0x0fa890d0
edit c0 d0 regs timing_cfg_3		0x00020000
edit c0 d0 regs ddr_sdram_cfg_2		0x24400010
edit c0 d0 regs ddr_sdram_mode		0x00401422
edit c0 d0 regs ddr_sdram_interval	0x61800100
edit c0 d0 regs ddr_data_init		0xdeadbeef
edit c0 d0 regs ddr_sdram_clk_cntl	0x02800000
edit c0 d0 regs timing_cfg_4		0x00220001
edit c0 d0 regs timing_cfg_5		0x03402400
edit c0 d0 regs ddr_zq_cntl		0x89080600
edit c0 d0 regs ddr_wrlvl_cntl		0x8655a608
edit c0 d0 regs err_int_en		0x0000000d
edit c0 d0 regs ddr_cdr1		0x000c0000
edit c0 d0 regs ddr_cdr2		0x00000000
edit c0 d0 regs ddr_sdram_cfg		0xe7000008
go

I get this message:
2 GiB (DDR2, 64-bit, CL=0.5, ECC off)

Basically completely wrong. It should be DDR3, CL=6, ECC on. That's what
happened before I tried to use the SPD.

I could use some pointers on how to debug this.

Ira

> > On Fri, 2011-11-11 at 14:54 -0800, McClintock Matthew-B29882 wrote:
> > > Adding York who might be able to help more...
> > > 
> > > -M
> > > 
> > > On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > > > On Fri, Nov 11, 2011 at 09:07:23PM +0000, McClintock Matthew-B29882 wrote:
> > > >> On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
> > > >> > Thanks. That config_sram.dat is exactly what I came up with.
> > > >> >
> > > >> > I have my board booting via L2SRAM, but the DDR doesn't get configured
> > > >> > correctly yet. I'm trying to figure out how the DDR SPD stuff works in
> > > >> > U-Boot. I've never used it before. I'm following the P2020DS code as an
> > > >> > example, but I haven't yet figured out how the code in
> > > >> > board/freescale/p2020ds/ddr.c was derived (the board_specific_parameters
> > > >> > structure especially).
> > > >>
> > > >> If you board has i2c to the ddr modules it should be able to use the
> > > >> timing info from there. I think CONFIG_DDR_SPD is the config option
> > > >> you are looking for. I know the P2020DS does SPD from L2SRAM.
> > > >>
> > > >
> > > > The only thing that looks like an SPD chip is at i2c bus 1, address
> > > > 0x53. I setup my board configuration with:
> > > >
> > > > #define CONFIG_FSL_DDR3
> > > > #define CONFIG_FSL_DDR_INTERACTIVE
> > > > #define CONFIG_CHIP_SELECTS_PER_CTRL    2
> > > > #define CONFIG_SYS_DDR_SBE              0x00010000
> > > >
> > > > #define CONFIG_DDR_SPD
> > > > #define CONFIG_SYS_SPD_BUS_NUM          1
> > > > #define SPD_EEPROM_ADDRESS              0x53
> > > >
> > > > Some of the settings the SPD code computes are correct, and some are
> > > > completely wrong. I can't figure out how to make this work.
> > > >
> > > > Here is the raw SPD dumped from a working U-Boot:
> > > >
> > > > 0000: 92 10 0b 08 02 11 00 09 0b 52 01 08 0c 00 3e 00    .........R....>.
> > > > 0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 05    ixi0i. .p.<<....
> > > > 0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 1f 00    ................
> > > > 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 0070: 00 00 00 00 00 01 94 01 10 25 03 ae 48 48 e3 e3    .........%..HH..
> > > > 0080: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32    SG572568EMR069S2
> > > > 0090: 53 46 00 00 80 ce 53 4d 41 52 54 4d 6f 64 75 6c    SF....SMARTModul
> > > > 00a0: 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    arTechnologies..
> > > > 00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > > 00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
> > > >
> > > > And here is the output of an interactive FSL DDR run:
> > > >
> > > > U-Boot 2011.09-00929-g3b5f71c-dirty (Nov 11 2011 - 13:31:13)
> > > >
> > > > CPU0:  P2020E, Version: 2.0, (0x80ea0020)
> > > > Core:  E500, Version: 5.0, (0x80211050)
> > > > Clock Configuration:
> > > >       CPU0:1200 MHz, CPU1:1200 MHz,
> > > >       CCB:600  MHz,
> > > >       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500 MHz
> > > > L1:    D-cache 32 kB enabled
> > > >       I-cache 32 kB enabled
> > > > Board: Freescale COM Express P2020
> > > > I2C:   ready
> > > > SPI:   ready
> > > > DRAM:  FSL DDR>
> > > > FSL DDR>
> > > > FSL DDR>compute
> > > > unknown module_type 0x08
> > > > Detected UDIMM SG572568EMR069S2SF
> > > > The choosen cas latency 16 is too large
> > > > FSL DDR>print c0 d0
> > > > SPD info:  Controller=0 DIMM=0
> > > > 0      : 92 info_size_crc  bytes written into serial memory, CRC coverage
> > > > 1      : 10 spd_rev        SPD Revision
> > > > 2      : 0b mem_type       Key Byte / DRAM Device Type
> > > > 3      : 08 module_type    Key Byte / Module Type
> > > > 4      : 02 density_banks  SDRAM Density and Banks
> > > > 5      : 11 addressing     SDRAM Addressing
> > > > 6      : 00 module_vdd     Module Nominal Voltage, VDD
> > > > 7      : 09 organization   Module Organization
> > > > 8      : 0b bus_width      Module Memory Bus Width
> > > > 9      : 52 ftb_div        Fine Timebase (FTB) Dividend / Divisor
> > > > 10     : 01 mtb_dividend   Medium Timebase (MTB) Dividend
> > > > 11     : 08 mtb_divisor    Medium Timebase (MTB) Divisor
> > > > 12     : 0c tCK_min        SDRAM Minimum Cycle Time
> > > > 13     : 00 res_13         Reserved
> > > > 14     : 3e caslat_lsb     CAS Latencies Supported, LSB
> > > > 15     : 00 caslat_msb     CAS Latencies Supported, MSB
> > > > 16     : 69 tAA_min        Min CAS Latency Time
> > > > 17     : 78 tWR_min        Min Write REcovery Time
> > > > 18     : 69 tRCD_min       Min RAS# to CAS# Delay Time
> > > > 19     : 30 tRRD_min       Min Row Active to Row Active Delay Time
> > > > 20     : 69 tRP_min        Min Row Precharge Delay Time
> > > > 21     : 11 tRAS_tRC_ext   Upper Nibbles for tRAS and tRC
> > > > 22     : 20 tRAS_min_lsb   Min Active to Precharge Delay Time, LSB
> > > > 23     : 89 tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB
> > > > 24     : 70 tRFC_min_lsb   Min Refresh Recovery Delay Time LSB
> > > > 25     : 03 tRFC_min_msb   Min Refresh Recovery Delay Time MSB
> > > > 26     : 3c tWTR_min       Min Internal Write to Read Command Delay Time
> > > > 27     : 3c tRTP_min Min Internal Read to Precharge Command Delay Time
> > > > 28     : 00 tFAW_msb       Upper Nibble for tFAW
> > > > 29     : f0 tFAW_min       Min Four Activate Window Delay Time
> > > > 30     : 83 opt_features   SDRAM Optional Features
> > > > 31     : 05 therm_ref_opt  SDRAM Thermal and Refresh Opts
> > > > 32     : 80 therm_sensor  SDRAM Thermal Sensor
> > > > 33     : 00 device_type  SDRAM Device Type
> > > > 34 - 59: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > > > 60 -116: 0f111f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000117    : 01 Module MfgID Code LSB - JEP-106
> > > > 118    : 94 Module MfgID Code MSB - JEP-106
> > > > 119    : 01 Mfg Location
> > > > 120-121: 10 25 Mfg Date
> > > > 122-125: 03 ae 48 48    Module Serial Number
> > > > 126-127: e3 e3   SPD CRC
> > > > 128-145: 53 47 35 37 32 35 36 38 45 4d 52 30 36 39 53 32 53 46    Mfg's Module Part Number
> > > > 146-147: 00 00 Module Revision code
> > > > 148    : 80 DRAM MfgID Code LSB - JEP-106
> > > > 149    : ce DRAM MfgID Code MSB - JEP-106
> > > > 150-175: 53 4d 41 52 54 4d 6f 64 75 6c 61 72 54 65 63 68 6e 6f 6c 6f 67 69 65 73 00 00    Mfg's Specific Data
> > > > 176-255: 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000   Mfg's Specific Data
> > > >
> > > >
> > > >
> > > > DIMM parameters:  Controller=0 DIMM=0
> > > > DIMM organization parameters:
> > > > module part name = SG572568EMR069S2SF
> > > > rank_density = 1073741824 bytes (1024 megabytes)
> > > > capacity = 2147483648 bytes (2048 megabytes)
> > > > burst_lengths_bitmask = 00
> > > > base_addresss = 0 (00000000 00000000)
> > > > n_ranks = 2
> > > > data_width = 72
> > > > primary_sdram_width = 64
> > > > ec_sdram_width = 8
> > > > registered_dimm = 0
> > > > n_row_addr = 0
> > > > n_col_addr = 0
> > > > edc_config = 0
> > > > n_banks_per_sdram_device = 0
> > > > tCKmin_X_ps = 0
> > > > tCKmin_X_minus_1_ps = 0
> > > > tCKmin_X_minus_2_ps = 0
> > > > tCKmax_ps = 0
> > > > caslat_X = 0
> > > > tAA_ps = 0
> > > > caslat_X_minus_1 = 0
> > > > caslat_X_minus_2 = 0
> > > > caslat_lowest_derated = 0
> > > > tRCD_ps = 0
> > > > tRP_ps = 0
> > > > tRAS_ps = 0
> > > > tWR_ps = 0
> > > > tWTR_ps = 0
> > > > tRFC_ps = 0
> > > > tRRD_ps = 0
> > > > tRC_ps = 0
> > > > refresh_rate_ps = 0
> > > > tIS_ps = 0
> > > > tIH_ps = 0
> > > > tDS_ps = 0
> > > > tDH_ps = 0
> > > > tRTP_ps = 0
> > > > tDQSQ_max_ps = 0
> > > > tQHS_ps = 0
> > > >
> > > >
> > > >
> > > > "lowest common" DIMM parameters:  Controller=0
> > > > tCKmin_X_ps = 0 (4294967295 MHz)
> > > > tCKmax_ps = 0 (4294967295 MHz)
> > > > all_DIMMs_burst_lengths_bitmask = 00
> > > > tCKmax_max_ps = 0
> > > > tRCD_ps = 0
> > > > tRP_ps = 0
> > > > tRAS_ps = 0
> > > > tWR_ps = 0
> > > > tWTR_ps = 0
> > > > tRFC_ps = 0
> > > > tRRD_ps = 0
> > > > tRC_ps = 0
> > > > refresh_rate_ps = 0
> > > > tIS_ps = 0
> > > > tDS_ps = 0
> > > > tDH_ps = 0
> > > > tRTP_ps = 0
> > > > tDQSQ_max_ps = 0
> > > > tQHS_ps = 0
> > > > lowest_common_SPD_caslat = 0
> > > > highest_common_derated_caslat = 0
> > > > additive_latency = 0
> > > > ndimms_present = 1
> > > > all_DIMMs_registered = 0
> > > > all_DIMMs_unbuffered = 1
> > > > all_DIMMs_ECC_capable = 0
> > > > total_mem = 2147483648 (2048 megabytes)
> > > > base_address = 0 (0 megabytes)
> > > >
> > > >
> > > > User Config Options: Controller=0
> > > > cs0_odt_rd_cfg = 0
> > > > cs0_odt_wr_cfg = 1
> > > > cs1_odt_rd_cfg = 0
> > > > cs1_odt_wr_cfg = 1
> > > > cs0_odt_rtt_norm = 3
> > > > cs0_odt_rtt_wr = 0
> > > > cs1_odt_rtt_norm = 0
> > > > cs1_odt_rtt_wr = 0
> > > > memctl_interleaving = 0
> > > > memctl_interleaving_mode = 0
> > > > ba_intlv_ctl = 0x00000040
> > > > ECC_mode = 0
> > > > ECC_init_using_memctl = 1
> > > > DQS_config = 1
> > > > self_refresh_in_sleep = 1
> > > > dynamic_power = 0
> > > > data_bus_width = 0
> > > > burst_length = 6
> > > > cas_latency_override = 0
> > > > cas_latency_override_value = 3
> > > > use_derated_caslat = 0
> > > > additive_latency_override = 0
> > > > additive_latency_override_value = 3
> > > > clk_adjust = 6
> > > > cpo_override = 31
> > > > write_data_delay = 4
> > > > half_strength_driver_enable = 0
> > > > twoT_en = 0
> > > > threeT_en = 0
> > > > registered_dimm_en = 0
> > > > ap_en = 1
> > > > bstopre = 256
> > > > wrlvl_override = 1
> > > > wrlvl_sample = 10
> > > > wrlvl_start = 8
> > > > rcw_override = 0
> > > > rcw_1 = 0
> > > > rcw_2 = 0
> > > > tCKE_clock_pulse_width_ps = 9000
> > > > tFAW_window_four_activates_ps = 0
> > > > trwt_override = 0
> > > > trwt = 0
> > > >
> > > >
> > > > Address Assignment: Controller=0 DIMM=0
> > > > Don't have this functionality yet
> > > >
> > > >
> > > > Computed Register Values: Controller=0
> > > > cs0_bnds = 0x0000007F
> > > > cs0_config = 0x80014400
> > > > cs0_config_2 = 0x00000000
> > > > cs1_bnds = 0x00000000
> > > > cs1_config = 0x80014400
> > > > cs1_config_2 = 0x00000000
> > > > timing_cfg_3 = 0x000F0000
> > > > timing_cfg_0 = 0x40110104
> > > > timing_cfg_1 = 0x000F8246
> > > > timing_cfg_2 = 0x0FA8D0C0
> > > > ddr_sdram_cfg = 0xC7004000
> > > > ddr_sdram_cfg_2 = 0x24401040
> > > > ddr_sdram_mode = 0x00401021
> > > > ddr_sdram_mode_2 = 0x00000000
> > > > ddr_sdram_mode_3 = 0x00000000
> > > > ddr_sdram_mode_4 = 0x00000000
> > > > ddr_sdram_mode_5 = 0x00000000
> > > > ddr_sdram_mode_6 = 0x00000000
> > > > ddr_sdram_mode_7 = 0x00000000
> > > > ddr_sdram_mode_8 = 0x00000000
> > > > ddr_sdram_interval = 0x00000100
> > > > ddr_data_init = 0xDEADBEEF
> > > > ddr_sdram_clk_cntl = 0x03000000
> > > > ddr_init_addr = 0x00000000
> > > > ddr_init_ext_addr = 0x00000000
> > > > timing_cfg_4 = 0x00220001
> > > > timing_cfg_5 = 0x1C401400
> > > > ddr_zq_cntl = 0x89080600
> > > > ddr_wrlvl_cntl = 0x8675A608
> > > > ddr_sr_cntr = 0x00000000
> > > > ddr_sdram_rcw_1 = 0x00000000
> > > > ddr_sdram_rcw_2 = 0x00000000
> > > > ddr_cdr1 = 0x00000000
> > > > ddr_cdr2 = 0x00000000
> > > > err_disable = 0x00000000
> > > > err_int_en = 0x00000000
> > > > debug_01 = 0x00000000
> > > > debug_02 = 0x00000000
> > > > debug_03 = 0x00000000
> > > > debug_04 = 0x00000000
> > > > debug_05 = 0x00000000
> > > > debug_06 = 0x00000000
> > > > debug_07 = 0x00000000
> > > > debug_08 = 0x00000000
> > > > debug_09 = 0x00000000
> > > > debug_10 = 0x00000000
> > > > debug_11 = 0x00000000
> > > > debug_12 = 0x00000000
> > > > debug_13 = 0x00000000
> > > > debug_14 = 0x00000000
> > > > debug_15 = 0x00000000
> > > > debug_16 = 0x00000000
> > > > debug_17 = 0x00000000
> > > > debug_18 = 0x00000000
> > > > debug_19 = 0x00000000
> > > > debug_20 = 0x00000000
> > > > debug_21 = 0x00000000
> > > > debug_22 = 0x00000000
> > > > debug_23 = 0x00000000
> > > > debug_24 = 0x00000000
> > > > debug_25 = 0x00000000
> > > > debug_26 = 0x00000000
> > > > debug_27 = 0x00000000
> > > > debug_28 = 0x00000000
> > > > debug_29 = 0x00000000
> > > > debug_30 = 0x00000000
> > > > debug_31 = 0x00000000
> > > > debug_32 = 0x00000000
> > > >
> > > > _______________________________________________
> > > > U-Boot mailing list
> > > > U-Boot@lists.denx.de
> > > > http://lists.denx.de/mailman/listinfo/u-boot
> > > >
> > 
> > 
> > 
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

>>> 
>>> +phys_size_t fixed_sdram(void)
>>> +{
>>> +	char buf[32];
>>> +	fsl_ddr_cfg_regs_t ddr_cfg_regs;
>>> +	size_t ddr_size;
>>> +	struct cpu_type *cpu;
>>> +	ulong ddr_freq, ddr_freq_mhz;
>>> +
>>> +	cpu = gd->cpu;
>>> +	/* P1020 and it's derivatives support max 32bit DDR width */
>>> +	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
>>> +		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
>>> +		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
>> 
>> These checks don't make sense if you are a P2020 SoC
>> 
> 
> This entire file is identical to board/freescale/p1_p2_rdb/ddr.c. In
> fact, since this board only boots via the On-Chip ROM, the whole file is
> useless: fixed_sdram() should just return the RAM size. We're running
> from RAM when this function executes.
> 
> Is it ok with you if I replace the entire file with the following?
> 
> phys_size_t fixed_sdram(void)
> {
> 	return CONFIG_SYS_SDRAM_SIZE << 20;
> }

If the board has SO-DIMMs than I'd expect SPD support.  Sounds like you're working on this w/Matt & York.


>>> diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
>>> new file mode 100644
>>> index 0000000..56508db
>>> --- /dev/null
>>> +++ b/board/freescale/p2020come/law.c
>>> @@ -0,0 +1,36 @@
>>> +/*
>>> + * Copyright 2009 Freescale Semiconductor, Inc.
>>> + *
>>> + * See file CREDITS for list of people who contributed to this
>>> + * project.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>> + * MA 02111-1307 USA
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/fsl_law.h>
>>> +#include <asm/mmu.h>
>>> +
>>> +struct law_entry law_table[] = {
>>> +	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
>>> +	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
>>> +	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
>>> +	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
>>> +	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
>>> +	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
>> 
>> We normally set these up dynamically.
>> 
> 
> This is a modified version of the code from
> board/freescale/p1_p2_rdb/law.c. Can you suggest an in tree example of
> the way you'd like the code to look? I copied what I assume is a good
> example…

If you look at current board/freescale/p1_p2_rdb/law.c it doesn't have PCI LAWs anymore.  I think for your example you just need an empty data structure:

	struct law_entry law_table[] = {
	};

this should hopefully make num_law_entries = 0;


> 
>>> +};
>>> +
>>> +int num_law_entries = ARRAY_SIZE(law_table);
>>> diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
>>> new file mode 100644
>>> index 0000000..2e334cf
>>> --- /dev/null
>>> +++ b/board/freescale/p2020come/p2020come.c
>>> @@ -0,0 +1,401 @@
>>> +/*
>>> + * Copyright 2009 Freescale Semiconductor, Inc.
>>> + *
>>> + * See file CREDITS for list of people who contributed to this
>>> + * project.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>> + * MA 02111-1307 USA
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <hwconfig.h>
>>> +#include <command.h>
>>> +#include <asm/processor.h>
>>> +#include <asm/mmu.h>
>>> +#include <asm/cache.h>
>>> +#include <asm/immap_85xx.h>
>>> +#include <asm/fsl_serdes.h>
>>> +#include <asm/io.h>
>>> +#include <miiphy.h>
>>> +#include <libfdt.h>
>>> +#include <fdt_support.h>
>>> +#include <fsl_mdio.h>
>>> +#include <tsec.h>
>>> +#include <vsc7385.h>
>>> +#include <netdev.h>
>>> +#include <mmc.h>
>>> +#include <malloc.h>
>>> +#include <i2c.h>
>>> +
>>> +#if defined(CONFIG_PCI)
>>> +#include <asm/fsl_pci.h>
>>> +#include <pci.h>
>>> +#endif
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#if defined(CONFIG_PCI)
>>> +void pci_init_board(void)
>>> +{
>>> +	fsl_pcie_init_board(0);
>>> +}
>>> +
>>> +void ft_pci_board_setup(void *blob)
>>> +{
>>> +	FT_FSL_PCI_SETUP;
>>> +}
>>> +#endif
>>> +
>>> +/*
>>> + * GPIO
>>> + * 0 - 3: CarryBoard Input;
>>> + * 4 - 7: CarryBoard Output;
>>> + * 8 : Mux as SDHC_CD (card detection)
>>> + * 9 : Mux as SDHC_WP
>>> + * 10 : Clear Watchdog timer
>>> + * 11 : LED Input
>>> + * 12 : Output to 1
>>> + * 13 : Open Drain
>>> + * 14 : LED Output
>>> + * 15 : Switch Input
>>> + */
>>> +#define GPIO_DIR		0x0f3a0000
>>> +#define GPIO_ODR		0x00000000
>>> +
>>> +#define BOARD_PERI_RST_SET	(VSC7385_RST_SET | SLIC_RST_SET | \
>>> +				 SGMII_PHY_RST_SET | PCIE_RST_SET | \
>>> +				 RGMII_PHY_RST_SET)
>>> +
>>> +#define SYSCLK_MASK	0x00200000
>>> +#define BOARDREV_MASK	0x10100000
>>> +#define BOARDREV_B	0x10100000
>>> +#define BOARDREV_C	0x00100000
>>> +#define BOARDREV_D	0x00000000
>>> +
>>> +#define SYSCLK_66	66666666
>>> +#define SYSCLK_50	50000000
>>> +#define SYSCLK_100	100000000
>>> +
>>> +unsigned long get_board_sys_clk(ulong dummy)
>>> +{
>>> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>>> +	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
>>> +
>>> +	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
>>> +	switch (ddr_ratio) {
>>> +	case 0x0C:
>>> +		return SYSCLK_66;
>>> +	case 0x0A:
>>> +	case 0x08:
>>> +		return SYSCLK_100;
>>> +	default:
>>> +		puts("ERROR: unknown DDR ratio\n");
>>> +		return SYSCLK_100;
>>> +	}
>>> +}
>>> +
>>> +unsigned long get_board_ddr_clk(ulong dummy)
>>> +{
>>> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>>> +	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
>>> +
>>> +	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
>>> +	switch (ddr_ratio) {
>>> +	case 0x0C:
>>> +	case 0x0A:
>>> +		return SYSCLK_66;
>>> +	case 0x08:
>>> +		return SYSCLK_100;
>>> +	default:
>>> +		puts("ERROR: unknown DDR ratio\n");
>>> +		return SYSCLK_100;
>>> +	}
>>> +}
>>> +
>>> +#ifdef CONFIG_MMC
>>> +int board_early_init_f(void)
>>> +{
>>> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>>> +
>>> +	setbits_be32(&gur->pmuxcr,
>>> +			(MPC85xx_PMUXCR_SDHC_CD |
>>> +			 MPC85xx_PMUXCR_SDHC_WP));
>>> +
>>> +	/* All the device are enable except for SRIO12 */
>>> +	setbits_be32(&gur->devdisr, 0x80000);
>> 
>> Add a #define instead of magic 0x80000
>> 
>>> +	return 0;
>>> +}
>>> +#endif
>>> +
>>> +int checkboard(void)
>>> +{
>>> +	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
>>> +
>>> +	/*
>>> +	 * GPIO
>>> +	 * 0 - 3: CarryBoard Input;
>>> +	 * 4 - 7: CarryBoard Output;
>>> +	 * 8 : Mux as SDHC_CD (card detection)
>>> +	 * 9 : Mux as SDHC_WP
>>> +	 * 10 : Clear Watchdog timer
>>> +	 * 11 : LED Input
>>> +	 * 12 : Output to 1
>>> +	 * 13 : Open Drain
>>> +	 * 14 : LED Output
>>> +	 * 15 : Switch Input
>>> +	 *
>>> +	 * Set GPIOs 11, 12, 14 to 1.
>>> +	 */
>>> +	out_be32(&pgpio->gpdir, GPIO_DIR);
>>> +	out_be32(&pgpio->gpodr, GPIO_ODR);
>>> +	out_be32(&pgpio->gpdat, 0x001A0000);
>> 
>> look at using mpc85xx_gpio.h
>> 
> 
> Ok. This was copied from the BSP code. I'll change it to use the
> mpc85xx_gpio code.
> 
> While we're here, perhaps you can get the schematic for this board and
> see what the GPIO's are actually connected to. I can't get the
> schematic, so these comments are copied from the BSP code.

Is the schematic not provided?  Let me see if I can find someone familiar with this board.

> 
> The ones labeled "LED" (11 and 14) don't appear to change any LEDs that
> I can see on the board.
> 
>>> +
>>> +	puts("Board: Freescale COM Express P2020\n");
>>> +	return 0;
>>> +}
>>> +
>>> +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
>>> +
>>> +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
>>> +{
>>> +	u8 data;
>>> +
>>> +	if (i2c_read(0x68, reg, 1, &data, 1)) {
>>> +		M41ST85W_ERROR("unable to read %s bit\n", name);
>>> +		return;
>>> +	}
>>> +
>>> +	if (data & mask) {
>>> +		data &= ~mask;
>>> +		if (i2c_write(0x68, reg, 1, &data, 1)) {
>>> +			M41ST85W_ERROR("unable to clear %s bit\n", name);
>>> +			return;
>>> +		}
>>> +	}
>>> +}
>>> +
>>> +/*
>>> + * The P2020COME board has a STMicro M41ST85W RTC/watchdog
>>> + * at i2c bus 1 address 0x68.
>>> + */
>>> +static void start_rtc(void)
>>> +{
>>> +	unsigned int bus = i2c_get_bus_num();
>>> +
>>> +	if (i2c_set_bus_num(1)) {
>>> +		M41ST85W_ERROR("unable to set i2c bus\n");
>>> +		goto out;
>>> +	}
>>> +
>>> +	/* ensure ST (stop) and HT (halt update) bits are cleared */
>>> +	m41st85w_clear_bit(0x1, 0x80, "ST");
>>> +	m41st85w_clear_bit(0xc, 0x40, "HT");
>>> +
>>> +out:
>>> +	/* reset the i2c bus */
>>> +	i2c_set_bus_num(bus);
>>> +}
>>> +
>>> +int board_early_init_r(void)
>>> +{
>>> +	start_rtc();
>>> +	return 0;
>>> +}
>>> +
>>> +void board_reset(void)
>>> +{
>>> +	u8 data = (1 << 2) | 0x82;
>> 
>> some #defines instead of magic #s
>> 
>>> +
>>> +	/* set the hardware watchdog timeout to 1 second, then hang */
>>> +	i2c_set_bus_num(1);
>>> +	i2c_write(0x68, 9, 1, &data, 1);
>>> +
>>> +	while (1)
>>> +		/* hang */;
>>> +}
>>> +
>>> +#ifdef CONFIG_TSEC_ENET
>>> +int board_eth_init(bd_t *bis)
>>> +{
>>> +	struct fsl_pq_mdio_info mdio_info;
>>> +	struct tsec_info_struct tsec_info[4];
>>> +	int num = 0;
>>> +
>>> +#ifdef CONFIG_TSEC1
>>> +	SET_STD_TSEC_INFO(tsec_info[num], 1);
>>> +	num++;
>>> +#endif
>>> +#ifdef CONFIG_TSEC2
>>> +	SET_STD_TSEC_INFO(tsec_info[num], 2);
>>> +	num++;
>>> +#endif
>>> +#ifdef CONFIG_TSEC3
>>> +	SET_STD_TSEC_INFO(tsec_info[num], 3);
>>> +	if (is_serdes_configured(SGMII_TSEC3)) {
>>> +		puts("eTSEC3 is in sgmii mode.");
>>> +		tsec_info[num].flags |= TSEC_SGMII;
>>> +	}
>>> +	num++;
>>> +#endif
>>> +	if (!num) {
>>> +		printf("No TSECs initialized\n");
>>> +		return 0;
>>> +	}
>>> +
>>> +	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
>>> +	mdio_info.name = DEFAULT_MII_NAME;
>>> +	fsl_pq_mdio_init(bis, &mdio_info);
>>> +
>>> +	tsec_eth_init(bis, tsec_info, num);
>>> +
>>> +	return pci_eth_init(bis);
>>> +}
>>> +#endif
>>> +
>>> +#if defined(CONFIG_OF_BOARD_SETUP)
>>> +void fdt_fixup_add_2nd_usb(void *blob, int agent)
>>> +{
>> 
>> What are you trying to do here?
>> 
> 
> This was copied from the BSP code, I have no idea what the purpose is. I
> just checked: the board works fine with this removed. I'll remove it.
> 
>>> +	const char *soc_compat = "fsl,p2020-immr";
>>> +	const char *lbc_compat = "fsl,p2020-elbc";
>>> +	const u32 *addrcell, *sizecell, *ph;
>>> +	int off, lbcoff, len, err;
>>> +	u32 *regbuf = NULL;
>>> +	u32 *irqbuf = NULL;
>>> +
>>> +	off = fdt_node_offset_by_compatible(blob, -1, soc_compat);
>>> +	if (off < 0) {
>>> +		printf("WARNING: could not find compatible node %s: %s.\n",
>>> +			soc_compat, fdt_strerror(off));
>>> +		return;
>>> +	}
>>> +
>>> +	lbcoff = fdt_node_offset_by_compatible(blob, -1, lbc_compat);
>>> +	if (lbcoff < 0) {
>>> +		printf("WARNING: could not find compatible node %s: %s.\n",
>>> +			lbc_compat, fdt_strerror(lbcoff));
>>> +		return;
>>> +	}
>>> +
>>> +	addrcell = fdt_getprop(blob, off, "#address-cells", NULL);
>>> +	sizecell = fdt_getprop(blob, off, "#size-cells", NULL);
>>> +
>>> +	off = fdt_add_subnode(blob, off, "usb@23000");
>>> +	if (off < 0) {
>>> +		printf("WARNING: could not add 2nd usb node %s.\n",
>>> +				fdt_strerror(off));
>>> +		return;
>>> +	}
>>> +
>>> +	err = fdt_setprop_cell(blob, off, "#address-cells", 1);
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set #address-cell property: %s\n",
>>> +			fdt_strerror(err));
>>> +
>>> +	err = fdt_setprop_cell(blob, off, "#size-cells", 0);
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set #size-cells property: %s\n",
>>> +			fdt_strerror(err));
>>> +
>>> +	err = fdt_setprop_string(blob, off, "compatible", "fsl-usb2-dr");
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set compatible property: %s\n",
>>> +			fdt_strerror(err));
>>> +
>>> +	err = fdt_setprop_string(blob, off, "phy_type", "ulpi");
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set phy_type property: %s\n",
>>> +			fdt_strerror(err));
>>> +
>>> +	if (agent) {
>>> +		err = fdt_setprop_string(blob, off, "dr_mode", "peripheral");
>>> +		if (err < 0)
>>> +			printf("WARNING: could not set dr_mode property: %s\n",
>>> +				fdt_strerror(err));
>>> +	}
>>> +
>>> +	if (addrcell && *addrcell == 2) {
>>> +		regbuf[0] = 0;
>>> +		regbuf[1] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
>>> +		len = 2;
>>> +	} else {
>>> +		regbuf[0] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
>>> +		len = 1;
>>> +	}
>>> +
>>> +	if (sizecell && *sizecell == 2) {
>>> +		regbuf[len] = 0;
>>> +		regbuf[len + 1] = 0x1000;
>>> +		len = 2;
>>> +	} else {
>>> +		regbuf[len] = 0x1000;
>>> +		len++;
>>> +	}
>>> +
>>> +	err = fdt_setprop(blob, off, "reg", regbuf, len * sizeof(u32));
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set <%s> %s\n",
>>> +					"reg", fdt_strerror(err));
>>> +
>>> +	irqbuf[0] = 0x2e;
>>> +	irqbuf[1] = 0x2;
>>> +
>>> +	err = fdt_setprop(blob, off, "interrupts", irqbuf, 2 * sizeof(u32));
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set %s %s\n",
>>> +				"interrupts", fdt_strerror(err));
>>> +
>>> +	ph = fdt_getprop(blob, lbcoff, "interrupt-parent", 0);
>>> +	if (!ph) {
>>> +		printf("WARNING: could not read interrupt-parent property\n");
>>> +		return;
>>> +	}
>>> +
>>> +	err = fdt_setprop(blob, off, "interrupt-parent", ph, sizeof(u32));
>>> +	if (err < 0)
>>> +		printf("WARNING: could not set %s %s\n",
>>> +				"interrupt-parent", fdt_strerror(err));
>>> +}
>>> +
>>> +void ft_board_setup(void *blob, bd_t *bd)
>>> +{
>>> +	phys_addr_t base;
>>> +	phys_size_t size;
>>> +	int agent;
>>> +
>>> +	ft_cpu_setup(blob, bd);
>>> +
>>> +	base = getenv_bootm_low();
>>> +	size = getenv_bootm_size();
>>> +
>>> +#if defined(CONFIG_PCI)
>>> +	ft_pci_board_setup(blob);
>>> +#endif
>>> +
>>> +	fdt_fixup_memory(blob, (u64)base, (u64)size);
>>> +
>>> +	if (!hwconfig("usb2"))
>>> +		return;
>>> +
>>> +	agent = hwconfig_subarg_cmp("usb2", "dr_mode", "peripheral");
>>> +
>>> +	/*
>>> +	 * Add the 2nd usb node and enable it. eLBC will
>>> +	 * now be disabled since it is MUXed with USB2
>>> +	 */
>>> +
>>> +	fdt_fixup_add_2nd_usb(blob, agent);
>>> +}
>>> +#endif
>>> diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
>>> new file mode 100644
>>> index 0000000..e1dd056
>>> --- /dev/null
>>> +++ b/board/freescale/p2020come/tlb.c
>>> @@ -0,0 +1,100 @@
>>> +/*
>>> + * Copyright 2011 Freescale Semiconductor, Inc.
>>> + *
>>> + * See file CREDITS for list of people who contributed to this
>>> + * project.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>> + * MA 02111-1307 USA
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/mmu.h>
>>> +
>> 
>> For any regions that do NOT have code, we should remove MAS3_SX bit:
>> 
> 
> I assume you mean the CCSR and PCI regions. Maybe the
> CONFIG_SYS_INIT_RAM_ADDR regions too, I don't know what they're used
> for.

take a look at board/freescale/common/p_corenet/tlb.c

> 
> Thanks for the comments. I look forward to your feedback on the couple
> of questions I have.
> 
> Ira
> 
>>> +struct fsl_e_tlb_entry tlb_table[] = {
>>> +	/* TLB 0 - for temp stack in cache */
>>> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
>>> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
>>> +			0, 0, BOOKE_PAGESZ_4K, 0),
>>> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
>>> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
>>> +			0, 0, BOOKE_PAGESZ_4K, 0),
>>> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
>>> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
>>> +			0, 0, BOOKE_PAGESZ_4K, 0),
>>> +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
>>> +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, 0,
>>> +			0, 0, BOOKE_PAGESZ_4K, 0),
>>> +
>>> +	/* TLB 1 */
>>> +	/* *I*** - Covers boot page */
>>> +	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 0, BOOKE_PAGESZ_4K, 1),
>>> +
>>> +	/* *I*G* - CCSRBAR */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 1, BOOKE_PAGESZ_1M, 1),
>>> +
>>> +#if defined(CONFIG_PCI)
>>> +	/* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 2, BOOKE_PAGESZ_1G, 1),
>>> +
>>> +	/* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 3, BOOKE_PAGESZ_256M, 1),
>>> +
>>> +
>>> +	/* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
>>> +			CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 4, BOOKE_PAGESZ_256M, 1),
>>> +
>>> +	/*
>>> +	 * *I*G* - PCI I/O
>>> +	 *
>>> +	 * PCI3 => 0xFFC10000
>>> +	 * PCI2 => 0xFFC2,0000
>>> +	 * PCI1 => 0xFFC3,0000
>>> +	 */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 5, BOOKE_PAGESZ_256K, 1),
>>> +#endif /* #if defined(CONFIG_PCI) */
>>> +
>>> +#if defined(CONFIG_SYS_RAMBOOT)
>>> +	/* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 6, BOOKE_PAGESZ_1G, 1),
>>> +
>>> +	/*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
>>> +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
>>> +			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
>>> +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
>>> +			0, 7, BOOKE_PAGESZ_1G, 1),
>>> +#endif
>>> +};
>>> +
>>> +int num_tlb_entries = ARRAY_SIZE(tlb_table);
>> 
>> 
>>>

On Sat, Nov 12, 2011 at 12:16:05PM -0600, Kumar Gala wrote:
> > 
> > This entire file is identical to board/freescale/p1_p2_rdb/ddr.c. In
> > fact, since this board only boots via the On-Chip ROM, the whole file is
> > useless: fixed_sdram() should just return the RAM size. We're running
> > from RAM when this function executes.
> > 
> > Is it ok with you if I replace the entire file with the following?
> > 
> > phys_size_t fixed_sdram(void)
> > {
> > 	return CONFIG_SYS_SDRAM_SIZE << 20;
> > }
> 
> If the board has SO-DIMMs than I'd expect SPD support.  Sounds like you're working on this w/Matt & York.
> 

I don't need fixed_sdram() anymore. I figured out how to get L2 SRAM
boot working this week. Also, I finally tracked down a bug in the
Freescale DDR SPD code, exposed due to invalid data in the SPD. Darn
hardware manufacturers!

> >>> diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
> >>> new file mode 100644
> >>> index 0000000..56508db
> >>> --- /dev/null
> >>> +++ b/board/freescale/p2020come/law.c
> >>> @@ -0,0 +1,36 @@
> >>> +/*
> >>> + * Copyright 2009 Freescale Semiconductor, Inc.
> >>> + *
> >>> + * See file CREDITS for list of people who contributed to this
> >>> + * project.
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> + * modify it under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation; either version 2 of
> >>> + * the License, or (at your option) any later version.
> >>> + *
> >>> + * This program is distributed in the hope that it will be useful,
> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
> >>> + * GNU General Public License for more details.
> >>> + *
> >>> + * You should have received a copy of the GNU General Public License
> >>> + * along with this program; if not, write to the Free Software
> >>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >>> + * MA 02111-1307 USA
> >>> + */
> >>> +
> >>> +#include <common.h>
> >>> +#include <asm/fsl_law.h>
> >>> +#include <asm/mmu.h>
> >>> +
> >>> +struct law_entry law_table[] = {
> >>> +	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> >>> +	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> >>> +	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
> >>> +	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
> >>> +	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
> >>> +	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
> >> 
> >> We normally set these up dynamically.
> >> 
> > 
> > This is a modified version of the code from
> > board/freescale/p1_p2_rdb/law.c. Can you suggest an in tree example of
> > the way you'd like the code to look? I copied what I assume is a good
> > example…
> 
> If you look at current board/freescale/p1_p2_rdb/law.c it doesn't have PCI LAWs anymore.  I think for your example you just need an empty data structure:
> 
> 	struct law_entry law_table[] = {
> 	};
> 
> this should hopefully make num_law_entries = 0;
> 
> 
> > 
> >>> +};
> >>> +
> >>> +int num_law_entries = ARRAY_SIZE(law_table);

Unfortunately, having a law_table with no entries causes a bug. A nasty
bug which was hard to track down.

When law_table is empty, and when num_law_entries = 0, both variables
exist in BSS only.

Both the law_table and num_law_entries are used in init_laws(), called
from cpu_init_early_f(). This happens before BSS is initialized. Also
before DDR is initialized.

And now you see the bug. The U-Boot hangs due to an invalid memory
access. This is before the console is initialized, making it hard to
track down.

How do you suggest I work around this? A single redundant entry in the
law_table works (the system boots).

Thanks,
Ira

>> If you look at current board/freescale/p1_p2_rdb/law.c it doesn't have PCI LAWs anymore.  I think for your example you just need an empty data structure:
>> 
>> 	struct law_entry law_table[] = {
>> 	};
>> 
>> this should hopefully make num_law_entries = 0;
>> 
>> 
>>> 
>>>>> +};
>>>>> +
>>>>> +int num_law_entries = ARRAY_SIZE(law_table);
> 
> Unfortunately, having a law_table with no entries causes a bug. A nasty
> bug which was hard to track down.
> 
> When law_table is empty, and when num_law_entries = 0, both variables
> exist in BSS only.
> 
> Both the law_table and num_law_entries are used in init_laws(), called
> from cpu_init_early_f(). This happens before BSS is initialized. Also
> before DDR is initialized.
> 
> And now you see the bug. The U-Boot hangs due to an invalid memory
> access. This is before the console is initialized, making it hard to
> track down.

Yeah, that's nasty.  need to think on this a bit to see if I can come up with any good answer.

> How do you suggest I work around this? A single redundant entry in the
> law_table works (the system boots).

For now I'd go with that and add a comment in law.c about it.

- k