| Message ID | 1270734200-17762-10-git-send-email-rabin.vincent@stericsson.com |
|---|---|
| State | Not Applicable |
| Delegated to: | Albert ARIBAUD |
| Headers | show |
On 04/08/2010 08:43 AM, Rabin Vincent wrote: > Add Cortex A9 support by copying the code for Cortex A8. The only > change is a removal of some OMAP3 specific code. Thanks :), I was hoping to help in the near future by adding OMAP4 code in cortex a9.. ;) > > Acked-by: Michael Brandt<michael.brandt@stericsson.com> > Signed-off-by: Rabin Vincent<rabin.vincent@stericsson.com> > --- > cpu/{arm_cortexa8 => arm_cortexa9}/Makefile | 0 > cpu/{arm_cortexa8 => arm_cortexa9}/config.mk | 0 > cpu/{arm_cortexa8 => arm_cortexa9}/cpu.c | 0 > cpu/{arm_cortexa8 => arm_cortexa9}/start.S | 26 +------------------------ > cpu/{arm_cortexa8 => arm_cortexa9}/u-boot.lds | 2 +- > 5 files changed, 2 insertions(+), 26 deletions(-) > copy cpu/{arm_cortexa8 => arm_cortexa9}/Makefile (100%) > copy cpu/{arm_cortexa8 => arm_cortexa9}/config.mk (100%) > copy cpu/{arm_cortexa8 => arm_cortexa9}/cpu.c (100%) > copy cpu/{arm_cortexa8 => arm_cortexa9}/start.S (91%) > copy cpu/{arm_cortexa8 => arm_cortexa9}/u-boot.lds (97%) looking at the % of reuse.. for a9, cant we avoid a copy? since a9 and a8 are both v7 instruction set anyways, how about cpu/arm_cortexa8,a9 etc replaced by cpu/armv7 and have cortex and soc specific code within it? option a: cpu/armv7/ common code.[cS..] /cortex_a8/ /cortex_a9/ soc specific code: option 1: cpu/armv7/cortex_a[89]/soc or option 2: cpu/armv7/soc option b: cpu/armv7_common/ cpu/cortex_a8/ cpu/cortex_a9/ (socs thier usual place cpu/cortex_a[89]/socx option c: cpu/armv7 cpu/armv7/soc1 cpu/armv7/soc2 etc.. v7 has both a8 and a9 codebases.. Regards, Nishanth Menon
On Fri, Apr 9, 2010 at 4:59 PM, Nishanth Menon <menon.nishanth@gmail.com>wrote: > On 04/08/2010 08:43 AM, Rabin Vincent wrote: > > Add Cortex A9 support by copying the code for Cortex A8. The only > > change is a removal of some OMAP3 specific code. > Thanks :), I was hoping to help in the near future by adding OMAP4 code > in cortex a9.. ;) > > > > > Acked-by: Michael Brandt<michael.brandt@stericsson.com> > > Signed-off-by: Rabin Vincent<rabin.vincent@stericsson.com> > > --- > > cpu/{arm_cortexa8 => arm_cortexa9}/Makefile | 0 > > cpu/{arm_cortexa8 => arm_cortexa9}/config.mk | 0 > > cpu/{arm_cortexa8 => arm_cortexa9}/cpu.c | 0 > > cpu/{arm_cortexa8 => arm_cortexa9}/start.S | 26 > +------------------------ > > cpu/{arm_cortexa8 => arm_cortexa9}/u-boot.lds | 2 +- > > 5 files changed, 2 insertions(+), 26 deletions(-) > > copy cpu/{arm_cortexa8 => arm_cortexa9}/Makefile (100%) > > copy cpu/{arm_cortexa8 => arm_cortexa9}/config.mk (100%) > > copy cpu/{arm_cortexa8 => arm_cortexa9}/cpu.c (100%) > > copy cpu/{arm_cortexa8 => arm_cortexa9}/start.S (91%) > > copy cpu/{arm_cortexa8 => arm_cortexa9}/u-boot.lds (97%) > > looking at the % of reuse.. for a9, cant we avoid a copy? since a9 and > a8 are both v7 instruction set anyways, > > how about cpu/arm_cortexa8,a9 etc replaced by cpu/armv7 and have cortex > and soc specific code within it? > > Making the folders based on ISA version would be confusing as the other ARM cores are not grouped that way. As all Cortex processors implement the ARMv7 architecture a better grouping IMHO would be cpu/cortex/a8 and cpu/cortex/a9. The common stuff can be under cpu/cortex/. > option a: > cpu/armv7/ > common code.[cS..] > /cortex_a8/ > /cortex_a9/ > soc specific code: > option 1: > cpu/armv7/cortex_a[89]/soc > or option 2: > cpu/armv7/soc > > option b: > cpu/armv7_common/ > cpu/cortex_a8/ > cpu/cortex_a9/ > > (socs thier usual place cpu/cortex_a[89]/socx > option c: > cpu/armv7 > cpu/armv7/soc1 > cpu/armv7/soc2 > etc.. > v7 has both a8 and a9 codebases.. > > Regards, > Nishanth Menon > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot >
Dear Vaibhav Bedia, In message <q2ybaa2b3351004090627jecaaf94byd1e5edf46e0644d@mail.gmail.com> you wrote: > > > Making the folders based on ISA version would be confusing as the other ARM > cores are not grouped that way. > As all Cortex processors implement the ARMv7 architecture a better grouping > IMHO would be cpu/cortex/a8 and cpu/cortex/a9. The common stuff can be under > cpu/cortex/. Sounds good to me. Best regards, Wolfgang Denk
On Fri, Apr 9, 2010 at 6:57 PM, Vaibhav Bedia <vaibhav.bedia@gmail.com> wrote: > As all Cortex processors implement the ARMv7 architecture a better grouping > IMHO would be cpu/cortex/a8 and cpu/cortex/a9. The common stuff can be under > cpu/cortex/. Perhaps Tom can clarify if he's OK with this, since he wanted a separate cpu/cortex_a9 directory to be created (The first version of my patch series just put the Ux500 code into cortex_a8). The only potential problem I see with this is that some fixups will have to be done in the Makefiles for lib$(CPU).a generation since $(CPU) would have a slash in it after this. This could be avoided by keeping the SOC directories for all Cortexes in cpu/arm_cortex itself instead of a8 and a9 subdirectories. Rabin
Hi Tom, On Sun, Apr 11, 2010 at 10:45:41PM +0200, Tom wrote: > Rabin Vincent wrote: > > On Fri, Apr 9, 2010 at 6:57 PM, Vaibhav Bedia <vaibhav.bedia@gmail.com> wrote: > >> As all Cortex processors implement the ARMv7 architecture a better grouping > >> IMHO would be cpu/cortex/a8 and cpu/cortex/a9. The common stuff can be under > >> cpu/cortex/. > > > > Perhaps Tom can clarify if he's OK with this, since he wanted a separate > > cpu/cortex_a9 directory to be created (The first version of my patch series > > just put the Ux500 code into cortex_a8). > > > > The only potential problem I see with this is that some fixups will have to be > > done in the Makefiles for lib$(CPU).a generation since $(CPU) would have a > > slash in it after this. This could be avoided by keeping the SOC directories > > for all Cortexes in cpu/arm_cortex itself instead of a8 and a9 subdirectories. > > > > Rabin > > The change the Nishanth proposed is better. > I am ok with this change. > > My concern with the original Ux500 code was not to include a9 in a8. > As this would in the long run make for less readable and less maintainable code. > The new change would mean less copying of files but more reordering. > > I would suggest that 'fix me' warnings would be added to the a8 boards to defer > the reordering. The reordering need not all in the ux500 patchset. If you want > to take up all the reordering, that is fine too. I've posted a set of patches which adds the Makefile modifications necessary to support this directory structure, and also moves all Cortex-A8 SOCs into the new locations. If you find those patches acceptable, I'll rebase the Ux500 patchset based on top of that. Rabin
diff --git a/cpu/arm_cortexa8/Makefile b/cpu/arm_cortexa9/Makefile similarity index 100% copy from cpu/arm_cortexa8/Makefile copy to cpu/arm_cortexa9/Makefile diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa9/config.mk similarity index 100% copy from cpu/arm_cortexa8/config.mk copy to cpu/arm_cortexa9/config.mk diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa9/cpu.c similarity index 100% copy from cpu/arm_cortexa8/cpu.c copy to cpu/arm_cortexa9/cpu.c diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa9/start.S similarity index 91% copy from cpu/arm_cortexa8/start.S copy to cpu/arm_cortexa9/start.S index 29dae2f..d667f6e 100644 --- a/cpu/arm_cortexa8/start.S +++ b/cpu/arm_cortexa9/start.S @@ -1,5 +1,5 @@ /* - * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core + * armboot - Startup Code for ARM Cortex-A9 CPU-core * * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> * @@ -108,30 +108,6 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0 -#if (CONFIG_OMAP34XX) - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start @ r0 <- current position of code - add r0, r0, #4 @ skip reset vector - mov r2, #64 @ r2 <- size to copy - add r2, r0, r2 @ r2 <- source end address - mov r1, #SRAM_OFFSET0 @ build vect addr - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3 - r10} @ copy from source address [r0] - stmia r1!, {r3 - r10} @ copy to target address [r1] - cmp r0, r2 @ until source end address [r2] - bne next @ loop until equal */ -#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) - /* No need to copy/exec the clock code - DPLL adjust already done - * in NAND/oneNAND Boot. - */ - bl cpy_clk_code @ put dpll adjust code behind vectors -#endif /* NAND Boot */ -#endif - /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif diff --git a/cpu/arm_cortexa8/u-boot.lds b/cpu/arm_cortexa9/u-boot.lds similarity index 97% copy from cpu/arm_cortexa8/u-boot.lds copy to cpu/arm_cortexa9/u-boot.lds index 4f1711c..fc787cd 100644 --- a/cpu/arm_cortexa8/u-boot.lds +++ b/cpu/arm_cortexa9/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS . = ALIGN(4); .text : { - cpu/arm_cortexa8/start.o (.text) + cpu/arm_cortexa9/start.o (.text) *(.text) }