| Message ID | 095bc928555e089fd42796ed623cc7a3ce9138c4.1603116530.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | b79a7030c31d4fdc3d37e41391a8272bc7f0f21a |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | [v2] spi: zynq_spi: Use clk subsystem to get reference spi clk | expand |
po 19. 10. 2020 v 16:08 odesÃlatel Michal Simek <michal.simek@xilinx.com> napsal: > > From: T Karthik Reddy <t.karthik.reddy@xilinx.com> > > Remove fixed reference clk used by plat->frequency and use clk > subsystem to get reference clk. As per spi dt bindings > "spi-max-frequency" property should be used by the slave devices. > This property is read by spi-uclass driver for the slave device. > So avoid reading above property from the platform driver. > > Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > Changes in v2: > - Fix dev_err message first parameter and add missing header > > drivers/spi/zynq_spi.c | 35 ++++++++++++++++++++++++++++------- > 1 file changed, 28 insertions(+), 7 deletions(-) > > diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c > index 9923931e36ec..cb911c34f68d 100644 > --- a/drivers/spi/zynq_spi.c > +++ b/drivers/spi/zynq_spi.c > @@ -8,10 +8,12 @@ > > #include <common.h> > #include <dm.h> > +#include <dm/device_compat.h> > #include <log.h> > #include <malloc.h> > #include <spi.h> > #include <time.h> > +#include <clk.h> > #include <asm/io.h> > #include <linux/bitops.h> > #include <linux/delay.h> > @@ -79,17 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus) > > plat->regs = dev_read_addr_ptr(bus); > > - /* FIXME: Use 250MHz as a suitable default */ > - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", > - 250000000); > plat->deactivate_delay_us = fdtdec_get_int(blob, node, > "spi-deactivate-delay", 0); > plat->activate_delay_us = fdtdec_get_int(blob, node, > "spi-activate-delay", 0); > - plat->speed_hz = plat->frequency / 2; > - > - debug("%s: regs=%p max-frequency=%d\n", __func__, > - plat->regs, plat->frequency); > > return 0; > } > @@ -128,13 +123,39 @@ static int zynq_spi_probe(struct udevice *bus) > { > struct zynq_spi_platdata *plat = dev_get_platdata(bus); > struct zynq_spi_priv *priv = dev_get_priv(bus); > + struct clk clk; > + unsigned long clock; > + int ret; > > priv->regs = plat->regs; > priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; > > + ret = clk_get_by_name(bus, "ref_clk", &clk); > + if (ret < 0) { > + dev_err(bus, "failed to get clock\n"); > + return ret; > + } > + > + clock = clk_get_rate(&clk); > + if (IS_ERR_VALUE(clock)) { > + dev_err(bus, "failed to get rate\n"); > + return clock; > + } > + > + ret = clk_enable(&clk); > + if (ret && ret != -ENOSYS) { > + dev_err(bus, "failed to enable clock\n"); > + return ret; > + } > + > /* init the zynq spi hw */ > zynq_spi_init_hw(priv); > > + plat->frequency = clock; > + plat->speed_hz = plat->frequency / 2; > + > + debug("%s: max-frequency=%d\n", __func__, plat->speed_hz); > + > return 0; > } > > -- > 2.28.0 > Applied. M
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 9923931e36ec..cb911c34f68d 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -8,10 +8,12 @@ #include <common.h> #include <dm.h> +#include <dm/device_compat.h> #include <log.h> #include <malloc.h> #include <spi.h> #include <time.h> +#include <clk.h> #include <asm/io.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -79,17 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus) plat->regs = dev_read_addr_ptr(bus); - /* FIXME: Use 250MHz as a suitable default */ - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 250000000); plat->deactivate_delay_us = fdtdec_get_int(blob, node, "spi-deactivate-delay", 0); plat->activate_delay_us = fdtdec_get_int(blob, node, "spi-activate-delay", 0); - plat->speed_hz = plat->frequency / 2; - - debug("%s: regs=%p max-frequency=%d\n", __func__, - plat->regs, plat->frequency); return 0; } @@ -128,13 +123,39 @@ static int zynq_spi_probe(struct udevice *bus) { struct zynq_spi_platdata *plat = dev_get_platdata(bus); struct zynq_spi_priv *priv = dev_get_priv(bus); + struct clk clk; + unsigned long clock; + int ret; priv->regs = plat->regs; priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; + ret = clk_get_by_name(bus, "ref_clk", &clk); + if (ret < 0) { + dev_err(bus, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(bus, "failed to get rate\n"); + return clock; + } + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(bus, "failed to enable clock\n"); + return ret; + } + /* init the zynq spi hw */ zynq_spi_init_hw(priv); + plat->frequency = clock; + plat->speed_hz = plat->frequency / 2; + + debug("%s: max-frequency=%d\n", __func__, plat->speed_hz); + return 0; }