| Message ID | 20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de |
|---|---|
| Headers | show |
| Series | SMP support for RISC-V | expand |
> -----Original Message----- > From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > Sent: Wednesday, March 6, 2019 4:23 AM > To: u-boot@lists.denx.de > Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel > <Anup.Patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Andreas > Schwab <schwab@suse.de>; Palmer Dabbelt <palmer@sifive.com>; > Alexander Graf <agraf@suse.de>; Lukas Auer > <lukas.auer@aisec.fraunhofer.de>; Anup Patel <Anup.Patel@wdc.com>; > Anup Patel <anup@brainfault.org>; Rick Chen <rick@andestech.com>; > Baruch Siach <baruch@tkos.co.il>; Atish Patra <Atish.Patra@wdc.com>; > Stefan Roese <sr@denx.de>; Paul Walmsley <paul.walmsley@sifive.com>; > Daniel Schwierzeck <daniel.schwierzeck@gmail.com> > Subject: [PATCH v2 0/9] SMP support for RISC-V > > This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to > run on multi-hart systems (hart is the RISC-V terminology for hardware > thread). Images passed to bootm will be started on all harts. > The bootm command is currently the only one that will boot images on all > harts, bootefi is not yet supported. > > The patches have been successfully tested on both QEMU (machine and > supervisor mode) and the HiFive Unleashed board (supervisor mode), using > BBL and OpenSBI. > Mainline QEMU requires two patches [1, 2] to run in this configuration. > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > Changes in v2: > - Remove unneeded quotes from NR_CPUS Kconfig entry > - Move memory barrier from send_ipi_many() to handle_ipi() > - Add check in send_ipi_many so that IPIs are only sent to available harts as > indicated by the available_harts mask > - Implement hart lottery to pick main hart to run U-Boot > - Remove CONFIG_MAIN_HART as it is not required anymore > - Register available harts in the available_harts mask > - New patch to populate register a0 with the hart ID from the mhartid CSR in > machine-mode > - New patch to enable SMP on the SiFive FU540, which was previously sent > independently > > Lukas Auer (9): > riscv: add infrastructure for calling functions on other harts > riscv: import the supervisor binary interface header file > riscv: implement IPI platform functions using SBI > riscv: delay initialization of caches and debug UART > riscv: add support for multi-hart systems > riscv: boot images passed to bootm on all harts > riscv: do not rely on hart ID passed by previous boot stage > riscv: fu540: enable SMP > riscv: qemu: enable SMP > > arch/riscv/Kconfig | 28 +++++ > arch/riscv/cpu/cpu.c | 9 +- > arch/riscv/cpu/start.S | 152 +++++++++++++++++++++++++-- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/global_data.h | 6 ++ > arch/riscv/include/asm/sbi.h | 94 +++++++++++++++++ > arch/riscv/include/asm/smp.h | 53 ++++++++++ > arch/riscv/lib/Makefile | 2 + > arch/riscv/lib/asm-offsets.c | 1 + > arch/riscv/lib/bootm.c | 13 ++- > arch/riscv/lib/sbi_ipi.c | 25 +++++ > arch/riscv/lib/smp.c | 116 ++++++++++++++++++++ > board/emulation/qemu-riscv/Kconfig | 1 + > board/sifive/fu540/Kconfig | 1 + > 14 files changed, 492 insertions(+), 10 deletions(-) create mode 100644 > arch/riscv/include/asm/sbi.h create mode 100644 > arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/lib/sbi_ipi.c > create mode 100644 arch/riscv/lib/smp.c > > -- > 2.20.1 I tried this series on U-Boot-2019.04-rc3 and works fine on SiFive Unleashed board. Tested-by: Anup Patel <anup.patel@wdc.com> I have also pushed these patches to riscv_sifive_fu540_smp_v4 branch of https://github.com/avpatel/u-boot.git Regards, Anup
On Wed, 2019-03-06 at 04:00 +0000, Anup Patel wrote: > > -----Original Message----- > > From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > Sent: Wednesday, March 6, 2019 4:23 AM > > To: u-boot@lists.denx.de > > Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel > > <Anup.Patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Andreas > > Schwab <schwab@suse.de>; Palmer Dabbelt <palmer@sifive.com>; > > Alexander Graf <agraf@suse.de>; Lukas Auer > > <lukas.auer@aisec.fraunhofer.de>; Anup Patel <Anup.Patel@wdc.com>; > > Anup Patel <anup@brainfault.org>; Rick Chen <rick@andestech.com>; > > Baruch Siach <baruch@tkos.co.il>; Atish Patra <Atish.Patra@wdc.com> > > ; > > Stefan Roese <sr@denx.de>; Paul Walmsley <paul.walmsley@sifive.com> > > ; > > Daniel Schwierzeck <daniel.schwierzeck@gmail.com> > > Subject: [PATCH v2 0/9] SMP support for RISC-V > > > > This patch series adds SMP support for RISC-V to U-Boot. It allows > > U-Boot to > > run on multi-hart systems (hart is the RISC-V terminology for > > hardware > > thread). Images passed to bootm will be started on all harts. > > The bootm command is currently the only one that will boot images > > on all > > harts, bootefi is not yet supported. > > > > The patches have been successfully tested on both QEMU (machine and > > supervisor mode) and the HiFive Unleashed board (supervisor mode), > > using > > BBL and OpenSBI. > > Mainline QEMU requires two patches [1, 2] to run in this > > configuration. > > > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > > > Changes in v2: > > - Remove unneeded quotes from NR_CPUS Kconfig entry > > - Move memory barrier from send_ipi_many() to handle_ipi() > > - Add check in send_ipi_many so that IPIs are only sent to > > available harts as > > indicated by the available_harts mask > > - Implement hart lottery to pick main hart to run U-Boot > > - Remove CONFIG_MAIN_HART as it is not required anymore > > - Register available harts in the available_harts mask > > - New patch to populate register a0 with the hart ID from the > > mhartid CSR in > > machine-mode > > - New patch to enable SMP on the SiFive FU540, which was previously > > sent > > independently > > > > Lukas Auer (9): > > riscv: add infrastructure for calling functions on other harts > > riscv: import the supervisor binary interface header file > > riscv: implement IPI platform functions using SBI > > riscv: delay initialization of caches and debug UART > > riscv: add support for multi-hart systems > > riscv: boot images passed to bootm on all harts > > riscv: do not rely on hart ID passed by previous boot stage > > riscv: fu540: enable SMP > > riscv: qemu: enable SMP > > > > arch/riscv/Kconfig | 28 +++++ > > arch/riscv/cpu/cpu.c | 9 +- > > arch/riscv/cpu/start.S | 152 > > +++++++++++++++++++++++++-- > > arch/riscv/include/asm/csr.h | 1 + > > arch/riscv/include/asm/global_data.h | 6 ++ > > arch/riscv/include/asm/sbi.h | 94 +++++++++++++++++ > > arch/riscv/include/asm/smp.h | 53 ++++++++++ > > arch/riscv/lib/Makefile | 2 + > > arch/riscv/lib/asm-offsets.c | 1 + > > arch/riscv/lib/bootm.c | 13 ++- > > arch/riscv/lib/sbi_ipi.c | 25 +++++ > > arch/riscv/lib/smp.c | 116 ++++++++++++++++++++ > > board/emulation/qemu-riscv/Kconfig | 1 + > > board/sifive/fu540/Kconfig | 1 + > > 14 files changed, 492 insertions(+), 10 deletions(-) create mode > > 100644 > > arch/riscv/include/asm/sbi.h create mode 100644 > > arch/riscv/include/asm/smp.h create mode 100644 > > arch/riscv/lib/sbi_ipi.c > > create mode 100644 arch/riscv/lib/smp.c > > > > -- > > 2.20.1 > > I tried this series on U-Boot-2019.04-rc3 and works fine on > SiFive Unleashed board. > > Tested-by: Anup Patel <anup.patel@wdc.com> > > I have also pushed these patches to riscv_sifive_fu540_smp_v4 > branch of https://github.com/avpatel/u-boot.git > Thank you for testing the series, Anup! Did you observe anymore issues, where not all harts enter Linux? Thanks, Lukas
> -----Original Message----- > From: Auer, Lukas <lukas.auer@aisec.fraunhofer.de> > Sent: Wednesday, March 6, 2019 2:52 PM > To: u-boot@lists.denx.de; Anup Patel <Anup.Patel@wdc.com> > Cc: paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; > baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; > rick@andestech.com; sr@denx.de; schwab@suse.de; palmer@sifive.com; > Atish Patra <Atish.Patra@wdc.com> > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > On Wed, 2019-03-06 at 04:00 +0000, Anup Patel wrote: > > > -----Original Message----- > > > From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > > Sent: Wednesday, March 6, 2019 4:23 AM > > > To: u-boot@lists.denx.de > > > Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel > > > <Anup.Patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Andreas > Schwab > > > <schwab@suse.de>; Palmer Dabbelt <palmer@sifive.com>; Alexander > Graf > > > <agraf@suse.de>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; Anup > > > Patel <Anup.Patel@wdc.com>; Anup Patel <anup@brainfault.org>; Rick > > > Chen <rick@andestech.com>; Baruch Siach <baruch@tkos.co.il>; Atish > > > Patra <Atish.Patra@wdc.com> ; Stefan Roese <sr@denx.de>; Paul > > > Walmsley <paul.walmsley@sifive.com> ; Daniel Schwierzeck > > > <daniel.schwierzeck@gmail.com> > > > Subject: [PATCH v2 0/9] SMP support for RISC-V > > > > > > This patch series adds SMP support for RISC-V to U-Boot. It allows > > > U-Boot to run on multi-hart systems (hart is the RISC-V terminology > > > for hardware thread). Images passed to bootm will be started on all > > > harts. > > > The bootm command is currently the only one that will boot images on > > > all harts, bootefi is not yet supported. > > > > > > The patches have been successfully tested on both QEMU (machine and > > > supervisor mode) and the HiFive Unleashed board (supervisor mode), > > > using BBL and OpenSBI. > > > Mainline QEMU requires two patches [1, 2] to run in this > > > configuration. > > > > > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > > > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > > > > > Changes in v2: > > > - Remove unneeded quotes from NR_CPUS Kconfig entry > > > - Move memory barrier from send_ipi_many() to handle_ipi() > > > - Add check in send_ipi_many so that IPIs are only sent to available > > > harts as indicated by the available_harts mask > > > - Implement hart lottery to pick main hart to run U-Boot > > > - Remove CONFIG_MAIN_HART as it is not required anymore > > > - Register available harts in the available_harts mask > > > - New patch to populate register a0 with the hart ID from the > > > mhartid CSR in machine-mode > > > - New patch to enable SMP on the SiFive FU540, which was previously > > > sent independently > > > > > > Lukas Auer (9): > > > riscv: add infrastructure for calling functions on other harts > > > riscv: import the supervisor binary interface header file > > > riscv: implement IPI platform functions using SBI > > > riscv: delay initialization of caches and debug UART > > > riscv: add support for multi-hart systems > > > riscv: boot images passed to bootm on all harts > > > riscv: do not rely on hart ID passed by previous boot stage > > > riscv: fu540: enable SMP > > > riscv: qemu: enable SMP > > > > > > arch/riscv/Kconfig | 28 +++++ > > > arch/riscv/cpu/cpu.c | 9 +- > > > arch/riscv/cpu/start.S | 152 > > > +++++++++++++++++++++++++-- > > > arch/riscv/include/asm/csr.h | 1 + > > > arch/riscv/include/asm/global_data.h | 6 ++ > > > arch/riscv/include/asm/sbi.h | 94 +++++++++++++++++ > > > arch/riscv/include/asm/smp.h | 53 ++++++++++ > > > arch/riscv/lib/Makefile | 2 + > > > arch/riscv/lib/asm-offsets.c | 1 + > > > arch/riscv/lib/bootm.c | 13 ++- > > > arch/riscv/lib/sbi_ipi.c | 25 +++++ > > > arch/riscv/lib/smp.c | 116 ++++++++++++++++++++ > > > board/emulation/qemu-riscv/Kconfig | 1 + > > > board/sifive/fu540/Kconfig | 1 + > > > 14 files changed, 492 insertions(+), 10 deletions(-) create mode > > > 100644 > > > arch/riscv/include/asm/sbi.h create mode 100644 > > > arch/riscv/include/asm/smp.h create mode 100644 > > > arch/riscv/lib/sbi_ipi.c create mode 100644 arch/riscv/lib/smp.c > > > > > > -- > > > 2.20.1 > > > > I tried this series on U-Boot-2019.04-rc3 and works fine on SiFive > > Unleashed board. > > > > Tested-by: Anup Patel <anup.patel@wdc.com> > > > > I have also pushed these patches to riscv_sifive_fu540_smp_v4 branch > > of https://github.com/avpatel/u-boot.git > > > > Thank you for testing the series, Anup! > Did you observe anymore issues, where not all harts enter Linux? I tried using cold-boot (using power-on button) worked fine for me 10 times. I did not try more. We are trying to make OpenSBI stable with warm-boot (using reset button) as well but I have not tried that with U-Boot using reset button. Regards, Anup > > Thanks, > Lukas
Apparently sometimes u-boot tries to boot the kernel on heart 0 (the E51 core), which will then fail to start userspace, since that cannot cope with the missing fpu. Andreas.
> -----Original Message----- > From: Andreas Schwab <schwab@suse.de> > Sent: Wednesday, March 6, 2019 4:27 PM > To: Anup Patel <Anup.Patel@wdc.com> > Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; u-boot@lists.denx.de; > paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; > baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; > rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish Patra > <Atish.Patra@wdc.com> > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > Apparently sometimes u-boot tries to boot the kernel on heart 0 (the E51 > core), which will then fail to start userspace, since that cannot cope with the > missing fpu. That's not possible because in this series we have "available_hart_mask" to track HARTs that entered U-Boot. Recently, Atish made some progress with OpenSBI warm-boot issues. I will let him provide details about it. Regards, Anup
On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: >> -----Original Message----- >> From: Andreas Schwab <schwab@suse.de> >> Sent: Wednesday, March 6, 2019 4:27 PM >> To: Anup Patel <Anup.Patel@wdc.com> >> Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; u-boot@lists.denx.de; >> paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; >> baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; >> rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish Patra >> <Atish.Patra@wdc.com> >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V >> >> Apparently sometimes u-boot tries to boot the kernel on heart 0 (the E51 >> core), which will then fail to start userspace, since that cannot cope with the >> missing fpu. > > That's not possible Yes, it is. OpenSBI v0.3 (Mar 6 2019 10:55:01) ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : SiFive Freedom U540 Platform HART Features : RV64ACDFIMSU Platform Max HARTs : 5 Current Hart : 2 Firmware Base : 0x80000000 Firmware Size : 88 KB Runtime SBI Version : 0.1 PMP0: 0x0000000080000000-0x000000008001ffff (A) PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 +0100) CPU: rv64imac Model: sifive,hifive-unleashed-a00 DRAM: 8 GiB Andreas.
On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab@suse.de> wrote: > > On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > > >> -----Original Message----- > >> From: Andreas Schwab <schwab@suse.de> > >> Sent: Wednesday, March 6, 2019 4:27 PM > >> To: Anup Patel <Anup.Patel@wdc.com> > >> Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; u-boot@lists.denx.de; > >> paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; > >> baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; > >> rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish Patra > >> <Atish.Patra@wdc.com> > >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > >> > >> Apparently sometimes u-boot tries to boot the kernel on heart 0 (the E51 > >> core), which will then fail to start userspace, since that cannot cope with the > >> missing fpu. > > > > That's not possible > > Yes, it is. > > > OpenSBI v0.3 (Mar 6 2019 10:55:01) > ____ _____ ____ _____ > / __ \ / ____| _ \_ _| > | | | |_ __ ___ _ __ | (___ | |_) || | > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > | |__| | |_) | __/ | | |____) | |_) || |_ > \____/| .__/ \___|_| |_|_____/|____/_____| > | | > |_| > > Platform Name : SiFive Freedom U540 > Platform HART Features : RV64ACDFIMSU > Platform Max HARTs : 5 > Current Hart : 2 > Firmware Base : 0x80000000 > Firmware Size : 88 KB > Runtime SBI Version : 0.1 > > PMP0: 0x0000000080000000-0x000000008001ffff (A) > PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) > > > U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 +0100) > > CPU: rv64imac > Model: sifive,hifive-unleashed-a00 > DRAM: 8 GiB How does this prove that U-Boot is booting on HART 0? This seems to be warm reset issues for which fixes from Atish are not yet merged. Regards, Anup
On Mär 06 2019, Anup Patel <anup@brainfault.org> wrote: > On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab@suse.de> wrote: >> >> On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: >> >> >> -----Original Message----- >> >> From: Andreas Schwab <schwab@suse.de> >> >> Sent: Wednesday, March 6, 2019 4:27 PM >> >> To: Anup Patel <Anup.Patel@wdc.com> >> >> Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; u-boot@lists.denx.de; >> >> paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; >> >> baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; >> >> rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish Patra >> >> <Atish.Patra@wdc.com> >> >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V >> >> >> >> Apparently sometimes u-boot tries to boot the kernel on heart 0 (the E51 >> >> core), which will then fail to start userspace, since that cannot cope with the >> >> missing fpu. >> > >> > That's not possible >> >> Yes, it is. >> >> >> OpenSBI v0.3 (Mar 6 2019 10:55:01) >> ____ _____ ____ _____ >> / __ \ / ____| _ \_ _| >> | | | |_ __ ___ _ __ | (___ | |_) || | >> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | >> | |__| | |_) | __/ | | |____) | |_) || |_ >> \____/| .__/ \___|_| |_|_____/|____/_____| >> | | >> |_| >> >> Platform Name : SiFive Freedom U540 >> Platform HART Features : RV64ACDFIMSU >> Platform Max HARTs : 5 >> Current Hart : 2 >> Firmware Base : 0x80000000 >> Firmware Size : 88 KB >> Runtime SBI Version : 0.1 >> >> PMP0: 0x0000000080000000-0x000000008001ffff (A) >> PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) >> >> >> U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 +0100) >> >> CPU: rv64imac >> Model: sifive,hifive-unleashed-a00 >> DRAM: 8 GiB > > How does this prove that U-Boot is booting on HART 0? See the CPU isa. Andreas.
On Wed, 2019-03-06 at 13:01 +0100, Andreas Schwab wrote: > On Mär 06 2019, Anup Patel <anup@brainfault.org> wrote: > > > On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab@suse.de> > > wrote: > > > On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > > > > > > > > -----Original Message----- > > > > > From: Andreas Schwab <schwab@suse.de> > > > > > Sent: Wednesday, March 6, 2019 4:27 PM > > > > > To: Anup Patel <Anup.Patel@wdc.com> > > > > > Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; > > > > > u-boot@lists.denx.de; > > > > > paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; > > > > > baruch@tkos.co.il; daniel.schwierzeck@gmail.com; > > > > > bmeng.cn@gmail.com; > > > > > rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish > > > > > Patra > > > > > <Atish.Patra@wdc.com> > > > > > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > > > > > > > > > Apparently sometimes u-boot tries to boot the kernel on heart > > > > > 0 (the E51 > > > > > core), which will then fail to start userspace, since that > > > > > cannot cope with the > > > > > missing fpu. > > > > > > > > That's not possible > > > > > > Yes, it is. > > > > > > > > > OpenSBI v0.3 (Mar 6 2019 10:55:01) > > > ____ _____ ____ _____ > > > / __ \ / ____| _ \_ _| > > > | | | |_ __ ___ _ __ | (___ | |_) || | > > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > > > | |__| | |_) | __/ | | |____) | |_) || |_ > > > \____/| .__/ \___|_| |_|_____/|____/_____| > > > | | > > > |_| > > > > > > Platform Name : SiFive Freedom U540 > > > Platform HART Features : RV64ACDFIMSU > > > Platform Max HARTs : 5 > > > Current Hart : 2 > > > Firmware Base : 0x80000000 > > > Firmware Size : 88 KB > > > Runtime SBI Version : 0.1 > > > > > > PMP0: 0x0000000080000000-0x000000008001ffff (A) > > > PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) > > > > > > > > > U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 > > > +0100) > > > > > > CPU: rv64imac > > > Model: sifive,hifive-unleashed-a00 > > > DRAM: 8 GiB > > > > How does this prove that U-Boot is booting on HART 0? > > See the CPU isa. > Interesting.. U-Boot assumes that it can run on any core it is started on. In this case, OpenSBI must have booted its payload on hart 0. Lukas
On Wed, 2019-03-06 at 10:07 +0000, Anup Patel wrote: > > -----Original Message----- > > From: Auer, Lukas <lukas.auer@aisec.fraunhofer.de> > > Sent: Wednesday, March 6, 2019 2:52 PM > > To: u-boot@lists.denx.de; Anup Patel <Anup.Patel@wdc.com> > > Cc: paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; > > baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com > > ; > > rick@andestech.com; sr@denx.de; schwab@suse.de; palmer@sifive.com; > > Atish Patra <Atish.Patra@wdc.com> > > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > > > On Wed, 2019-03-06 at 04:00 +0000, Anup Patel wrote: > > > > -----Original Message----- > > > > From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > > > Sent: Wednesday, March 6, 2019 4:23 AM > > > > To: u-boot@lists.denx.de > > > > Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel > > > > <Anup.Patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Andreas > > Schwab > > > > <schwab@suse.de>; Palmer Dabbelt <palmer@sifive.com>; Alexander > > Graf > > > > <agraf@suse.de>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; > > > > Anup > > > > Patel <Anup.Patel@wdc.com>; Anup Patel <anup@brainfault.org>; > > > > Rick > > > > Chen <rick@andestech.com>; Baruch Siach <baruch@tkos.co.il>; > > > > Atish > > > > Patra <Atish.Patra@wdc.com> ; Stefan Roese <sr@denx.de>; Paul > > > > Walmsley <paul.walmsley@sifive.com> ; Daniel Schwierzeck > > > > <daniel.schwierzeck@gmail.com> > > > > Subject: [PATCH v2 0/9] SMP support for RISC-V > > > > > > > > This patch series adds SMP support for RISC-V to U-Boot. It > > > > allows > > > > U-Boot to run on multi-hart systems (hart is the RISC-V > > > > terminology > > > > for hardware thread). Images passed to bootm will be started on > > > > all > > > > harts. > > > > The bootm command is currently the only one that will boot > > > > images on > > > > all harts, bootefi is not yet supported. > > > > > > > > The patches have been successfully tested on both QEMU (machine > > > > and > > > > supervisor mode) and the HiFive Unleashed board (supervisor > > > > mode), > > > > using BBL and OpenSBI. > > > > Mainline QEMU requires two patches [1, 2] to run in this > > > > configuration. > > > > > > > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > > > > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > > > > > > > Changes in v2: > > > > - Remove unneeded quotes from NR_CPUS Kconfig entry > > > > - Move memory barrier from send_ipi_many() to handle_ipi() > > > > - Add check in send_ipi_many so that IPIs are only sent to > > > > available > > > > harts as indicated by the available_harts mask > > > > - Implement hart lottery to pick main hart to run U-Boot > > > > - Remove CONFIG_MAIN_HART as it is not required anymore > > > > - Register available harts in the available_harts mask > > > > - New patch to populate register a0 with the hart ID from the > > > > mhartid CSR in machine-mode > > > > - New patch to enable SMP on the SiFive FU540, which was > > > > previously > > > > sent independently > > > > > > > > Lukas Auer (9): > > > > riscv: add infrastructure for calling functions on other > > > > harts > > > > riscv: import the supervisor binary interface header file > > > > riscv: implement IPI platform functions using SBI > > > > riscv: delay initialization of caches and debug UART > > > > riscv: add support for multi-hart systems > > > > riscv: boot images passed to bootm on all harts > > > > riscv: do not rely on hart ID passed by previous boot stage > > > > riscv: fu540: enable SMP > > > > riscv: qemu: enable SMP > > > > > > > > arch/riscv/Kconfig | 28 +++++ > > > > arch/riscv/cpu/cpu.c | 9 +- > > > > arch/riscv/cpu/start.S | 152 > > > > +++++++++++++++++++++++++-- > > > > arch/riscv/include/asm/csr.h | 1 + > > > > arch/riscv/include/asm/global_data.h | 6 ++ > > > > arch/riscv/include/asm/sbi.h | 94 +++++++++++++++++ > > > > arch/riscv/include/asm/smp.h | 53 ++++++++++ > > > > arch/riscv/lib/Makefile | 2 + > > > > arch/riscv/lib/asm-offsets.c | 1 + > > > > arch/riscv/lib/bootm.c | 13 ++- > > > > arch/riscv/lib/sbi_ipi.c | 25 +++++ > > > > arch/riscv/lib/smp.c | 116 > > > > ++++++++++++++++++++ > > > > board/emulation/qemu-riscv/Kconfig | 1 + > > > > board/sifive/fu540/Kconfig | 1 + > > > > 14 files changed, 492 insertions(+), 10 deletions(-) create > > > > mode > > > > 100644 > > > > arch/riscv/include/asm/sbi.h create mode 100644 > > > > arch/riscv/include/asm/smp.h create mode 100644 > > > > arch/riscv/lib/sbi_ipi.c create mode 100644 > > > > arch/riscv/lib/smp.c > > > > > > > > -- > > > > 2.20.1 > > > > > > I tried this series on U-Boot-2019.04-rc3 and works fine on > > > SiFive > > > Unleashed board. > > > > > > Tested-by: Anup Patel <anup.patel@wdc.com> > > > > > > I have also pushed these patches to riscv_sifive_fu540_smp_v4 > > > branch > > > of https://github.com/avpatel/u-boot.git > > > > > > > Thank you for testing the series, Anup! > > Did you observe anymore issues, where not all harts enter Linux? > > I tried using cold-boot (using power-on button) worked fine for me > 10 times. I did not try more. > > We are trying to make OpenSBI stable with warm-boot (using reset > button) as well but I have not tried that with U-Boot using reset > button. > Great, so it seems the cold-boot issue is fixed now. Thanks for testing this! Lukas
On Wed, Mar 6, 2019 at 5:45 PM Auer, Lukas <lukas.auer@aisec.fraunhofer.de> wrote: > > On Wed, 2019-03-06 at 13:01 +0100, Andreas Schwab wrote: > > On Mär 06 2019, Anup Patel <anup@brainfault.org> wrote: > > > > > On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab@suse.de> > > > wrote: > > > > On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > > > > > > > > > > -----Original Message----- > > > > > > From: Andreas Schwab <schwab@suse.de> > > > > > > Sent: Wednesday, March 6, 2019 4:27 PM > > > > > > To: Anup Patel <Anup.Patel@wdc.com> > > > > > > Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; > > > > > > u-boot@lists.denx.de; > > > > > > paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; > > > > > > baruch@tkos.co.il; daniel.schwierzeck@gmail.com; > > > > > > bmeng.cn@gmail.com; > > > > > > rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish > > > > > > Patra > > > > > > <Atish.Patra@wdc.com> > > > > > > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > > > > > > > > > > > Apparently sometimes u-boot tries to boot the kernel on heart > > > > > > 0 (the E51 > > > > > > core), which will then fail to start userspace, since that > > > > > > cannot cope with the > > > > > > missing fpu. > > > > > > > > > > That's not possible > > > > > > > > Yes, it is. > > > > > > > > > > > > OpenSBI v0.3 (Mar 6 2019 10:55:01) > > > > ____ _____ ____ _____ > > > > / __ \ / ____| _ \_ _| > > > > | | | |_ __ ___ _ __ | (___ | |_) || | > > > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > > > > | |__| | |_) | __/ | | |____) | |_) || |_ > > > > \____/| .__/ \___|_| |_|_____/|____/_____| > > > > | | > > > > |_| > > > > > > > > Platform Name : SiFive Freedom U540 > > > > Platform HART Features : RV64ACDFIMSU > > > > Platform Max HARTs : 5 > > > > Current Hart : 2 > > > > Firmware Base : 0x80000000 > > > > Firmware Size : 88 KB > > > > Runtime SBI Version : 0.1 > > > > > > > > PMP0: 0x0000000080000000-0x000000008001ffff (A) > > > > PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) > > > > > > > > > > > > U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 > > > > +0100) > > > > > > > > CPU: rv64imac > > > > Model: sifive,hifive-unleashed-a00 > > > > DRAM: 8 GiB > > > > > > How does this prove that U-Boot is booting on HART 0? > > > > See the CPU isa. > > > > Interesting.. U-Boot assumes that it can run on any core it is started > on. In this case, OpenSBI must have booted its payload on hart 0. This is certainly not reproducible on cold-boot at my end but this does mean OpenSBI has booted HART0 and let it jump to U-Boot. Now OpenSBI (by default) on SiFive FU540 does not allow HART0 to go forward due to lack of S-mode. I think this is definitely the warm-boot issue where OpenSBI sees corrupted memory contents. Regards, Anup
On 3/6/19 4:32 AM, Anup Patel wrote: > On Wed, Mar 6, 2019 at 5:45 PM Auer, Lukas > <lukas.auer@aisec.fraunhofer.de> wrote: >> >> On Wed, 2019-03-06 at 13:01 +0100, Andreas Schwab wrote: >>> On Mär 06 2019, Anup Patel <anup@brainfault.org> wrote: >>> >>>> On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab@suse.de> >>>> wrote: >>>>> On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: >>>>> >>>>>>> -----Original Message----- >>>>>>> From: Andreas Schwab <schwab@suse.de> >>>>>>> Sent: Wednesday, March 6, 2019 4:27 PM >>>>>>> To: Anup Patel <Anup.Patel@wdc.com> >>>>>>> Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; >>>>>>> u-boot@lists.denx.de; >>>>>>> paul.walmsley@sifive.com; agraf@suse.de; anup@brainfault.org; >>>>>>> baruch@tkos.co.il; daniel.schwierzeck@gmail.com; >>>>>>> bmeng.cn@gmail.com; >>>>>>> rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish >>>>>>> Patra >>>>>>> <Atish.Patra@wdc.com> >>>>>>> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V >>>>>>> >>>>>>> Apparently sometimes u-boot tries to boot the kernel on heart >>>>>>> 0 (the E51 >>>>>>> core), which will then fail to start userspace, since that >>>>>>> cannot cope with the >>>>>>> missing fpu. >>>>>> >>>>>> That's not possible >>>>> >>>>> Yes, it is. >>>>> >>>>> >>>>> OpenSBI v0.3 (Mar 6 2019 10:55:01) >>>>> ____ _____ ____ _____ >>>>> / __ \ / ____| _ \_ _| >>>>> | | | |_ __ ___ _ __ | (___ | |_) || | >>>>> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | >>>>> | |__| | |_) | __/ | | |____) | |_) || |_ >>>>> \____/| .__/ \___|_| |_|_____/|____/_____| >>>>> | | >>>>> |_| >>>>> >>>>> Platform Name : SiFive Freedom U540 >>>>> Platform HART Features : RV64ACDFIMSU >>>>> Platform Max HARTs : 5 >>>>> Current Hart : 2 >>>>> Firmware Base : 0x80000000 >>>>> Firmware Size : 88 KB >>>>> Runtime SBI Version : 0.1 >>>>> >>>>> PMP0: 0x0000000080000000-0x000000008001ffff (A) >>>>> PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) >>>>> >>>>> >>>>> U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 >>>>> +0100) >>>>> >>>>> CPU: rv64imac >>>>> Model: sifive,hifive-unleashed-a00 >>>>> DRAM: 8 GiB >>>> >>>> How does this prove that U-Boot is booting on HART 0? >>> >>> See the CPU isa. >>> >> >> Interesting.. U-Boot assumes that it can run on any core it is started >> on. In this case, OpenSBI must have booted its payload on hart 0. > > This is certainly not reproducible on cold-boot at my end but this > does mean OpenSBI has booted HART0 and let it jump to U-Boot. > > Now OpenSBI (by default) on SiFive FU540 does not allow HART0 > to go forward due to lack of S-mode. I think this is definitely the > warm-boot issue where OpenSBI sees corrupted memory contents. > I am able to test both warm-boot and cold-boot several times(>10) without any issue with following pending PR in openSBI. https://github.com/riscv/opensbi/pull/84 @Andreas @Anup: Can you please apply the above PR on top of master and verify at your end as well? All the harts booted in Linux every time as well. Regards, Atish > Regards, > Anup >
> -----Original Message----- > From: Atish Patra <atish.patra@wdc.com> > Sent: Thursday, March 7, 2019 5:20 AM > To: Anup Patel <anup@brainfault.org>; Auer, Lukas > <lukas.auer@aisec.fraunhofer.de> > Cc: schwab@suse.de; paul.walmsley@sifive.com; agraf@suse.de; u- > boot@lists.denx.de; baruch@tkos.co.il; daniel.schwierzeck@gmail.com; > bmeng.cn@gmail.com; rick@andestech.com; sr@denx.de; > palmer@sifive.com; Anup Patel <Anup.Patel@wdc.com> > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > On 3/6/19 4:32 AM, Anup Patel wrote: > > On Wed, Mar 6, 2019 at 5:45 PM Auer, Lukas > > <lukas.auer@aisec.fraunhofer.de> wrote: > >> > >> On Wed, 2019-03-06 at 13:01 +0100, Andreas Schwab wrote: > >>> On Mär 06 2019, Anup Patel <anup@brainfault.org> wrote: > >>> > >>>> On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab@suse.de> > >>>> wrote: > >>>>> On Mär 06 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > >>>>> > >>>>>>> -----Original Message----- > >>>>>>> From: Andreas Schwab <schwab@suse.de> > >>>>>>> Sent: Wednesday, March 6, 2019 4:27 PM > >>>>>>> To: Anup Patel <Anup.Patel@wdc.com> > >>>>>>> Cc: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; > >>>>>>> u-boot@lists.denx.de; paul.walmsley@sifive.com; agraf@suse.de; > >>>>>>> anup@brainfault.org; baruch@tkos.co.il; > >>>>>>> daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; > >>>>>>> rick@andestech.com; sr@denx.de; palmer@sifive.com; Atish Patra > >>>>>>> <Atish.Patra@wdc.com> > >>>>>>> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > >>>>>>> > >>>>>>> Apparently sometimes u-boot tries to boot the kernel on heart > >>>>>>> 0 (the E51 > >>>>>>> core), which will then fail to start userspace, since that > >>>>>>> cannot cope with the missing fpu. > >>>>>> > >>>>>> That's not possible > >>>>> > >>>>> Yes, it is. > >>>>> > >>>>> > >>>>> OpenSBI v0.3 (Mar 6 2019 10:55:01) > >>>>> ____ _____ ____ _____ > >>>>> / __ \ / ____| _ \_ _| > >>>>> | | | |_ __ ___ _ __ | (___ | |_) || | > >>>>> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > >>>>> | |__| | |_) | __/ | | |____) | |_) || |_ > >>>>> \____/| .__/ \___|_| |_|_____/|____/_____| > >>>>> | | > >>>>> |_| > >>>>> > >>>>> Platform Name : SiFive Freedom U540 > >>>>> Platform HART Features : RV64ACDFIMSU > >>>>> Platform Max HARTs : 5 > >>>>> Current Hart : 2 > >>>>> Firmware Base : 0x80000000 > >>>>> Firmware Size : 88 KB > >>>>> Runtime SBI Version : 0.1 > >>>>> > >>>>> PMP0: 0x0000000080000000-0x000000008001ffff (A) > >>>>> PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X) > >>>>> > >>>>> > >>>>> U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 > >>>>> +0100) > >>>>> > >>>>> CPU: rv64imac > >>>>> Model: sifive,hifive-unleashed-a00 > >>>>> DRAM: 8 GiB > >>>> > >>>> How does this prove that U-Boot is booting on HART 0? > >>> > >>> See the CPU isa. > >>> > >> > >> Interesting.. U-Boot assumes that it can run on any core it is > >> started on. In this case, OpenSBI must have booted its payload on hart 0. > > > > This is certainly not reproducible on cold-boot at my end but this > > does mean OpenSBI has booted HART0 and let it jump to U-Boot. > > > > Now OpenSBI (by default) on SiFive FU540 does not allow HART0 to go > > forward due to lack of S-mode. I think this is definitely the > > warm-boot issue where OpenSBI sees corrupted memory contents. > > > > I am able to test both warm-boot and cold-boot several times(>10) without > any issue with following pending PR in openSBI. > > https://github.com/riscv/opensbi/pull/84 Thanks Atish, your changes have been merged in OpenSBI. > > @Andreas @Anup: Can you please apply the above PR on top of master and > verify at your end as well? > > All the harts booted in Linux every time as well. I tried warm-boot 10 times from U-Boot prompt and I did not see any issue at all. I also tried warm-boot 10 times from Linux prompt and I did not see any Issue at all. In both above cases, it came back to U-Boot prompt after warm-boot. Also, tried cold-boot couple of times. I works perfectly fine as well. Like I mentioned, there is no functional issue with this series. The warm-boot issues were fixed in OpenSBI. @Andreas, please try at your end. Regards, Anup
On Mär 07 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > Like I mentioned, there is no functional issue with this series. The > warm-boot issues were fixed in OpenSBI. > > @Andreas, please try at your end. As long as issue#65 isn't fixed opensbi is mostly a no-go for me. At least it gives me more reasons to press the reset button. :-) Andreas.
> -----Original Message----- > From: Andreas Schwab <schwab@suse.de> > Sent: Thursday, March 7, 2019 2:50 PM > To: Anup Patel <Anup.Patel@wdc.com> > Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel <anup@brainfault.org>; > Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; paul.walmsley@sifive.com; > agraf@suse.de; u-boot@lists.denx.de; baruch@tkos.co.il; > daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; > rick@andestech.com; sr@denx.de; palmer@sifive.com > Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > > On Mär 07 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > > > Like I mentioned, there is no functional issue with this series. The > > warm-boot issues were fixed in OpenSBI. > > > > @Andreas, please try at your end. > > As long as issue#65 isn't fixed opensbi is mostly a no-go for me. At least it > gives me more reasons to press the reset button. :-) The reset button works fine for me an Atish. I am sure it works fine for lot of other folks too. BTW, as-per discussion with SiFive folks the reset button on Unleashed Board is not much tested and it can misbehave on certain boards. It is quite possible that you might have a "flaky" board. Regards, Anup
On Mär 08 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > The reset button works fine for me an Atish. I am sure it works fine for lot of > other folks too. There is no issue with the reset button, only with openSBI. Andreas.
On Thu, 07 Mar 2019 19:37:30 PST (-0800), Anup Patel wrote: > > >> -----Original Message----- >> From: Andreas Schwab <schwab@suse.de> >> Sent: Thursday, March 7, 2019 2:50 PM >> To: Anup Patel <Anup.Patel@wdc.com> >> Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel <anup@brainfault.org>; >> Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; paul.walmsley@sifive.com; >> agraf@suse.de; u-boot@lists.denx.de; baruch@tkos.co.il; >> daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; >> rick@andestech.com; sr@denx.de; palmer@sifive.com >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V >> >> On Mär 07 2019, Anup Patel <Anup.Patel@wdc.com> wrote: >> >> > Like I mentioned, there is no functional issue with this series. The >> > warm-boot issues were fixed in OpenSBI. >> > >> > @Andreas, please try at your end. >> >> As long as issue#65 isn't fixed opensbi is mostly a no-go for me. At least it >> gives me more reasons to press the reset button. :-) > > The reset button works fine for me an Atish. I am sure it works fine for lot of > other folks too. > > BTW, as-per discussion with SiFive folks the reset button on Unleashed > Board is not much tested and it can misbehave on certain boards. It is quite > possible that you might have a "flaky" board. I don't think the reset button differs between boards. As far as I know, the issues are really just that it doesn't reset everything -- specifically some of the IP on the chip (clock, power, JTAG) isn't reset and nothing on the board (SD, ethernet, PCIe, etc) is reset. This frequently results in flakiness when debugging drivers, but the cores and memory system should all be OK. Is that issue 65 on github.com/opensbi? If so it clearly says this isn't a reset button issue.
> -----Original Message----- > From: Palmer Dabbelt <palmer@sifive.com> > Sent: Monday, March 11, 2019 5:26 PM > To: Anup Patel <Anup.Patel@wdc.com> > Cc: schwab@suse.de; Atish Patra <Atish.Patra@wdc.com>; > anup@brainfault.org; lukas.auer@aisec.fraunhofer.de; Paul Walmsley > <paul.walmsley@sifive.com>; agraf@suse.de; u-boot@lists.denx.de; > baruch@tkos.co.il; daniel.schwierzeck@gmail.com; bmeng.cn@gmail.com; > rick@andestech.com; sr@denx.de > Subject: RE: [PATCH v2 0/9] SMP support for RISC-V > > On Thu, 07 Mar 2019 19:37:30 PST (-0800), Anup Patel wrote: > > > > > >> -----Original Message----- > >> From: Andreas Schwab <schwab@suse.de> > >> Sent: Thursday, March 7, 2019 2:50 PM > >> To: Anup Patel <Anup.Patel@wdc.com> > >> Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel > >> <anup@brainfault.org>; Auer, Lukas <lukas.auer@aisec.fraunhofer.de>; > >> paul.walmsley@sifive.com; agraf@suse.de; u-boot@lists.denx.de; > >> baruch@tkos.co.il; daniel.schwierzeck@gmail.com; > bmeng.cn@gmail.com; > >> rick@andestech.com; sr@denx.de; palmer@sifive.com > >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V > >> > >> On Mär 07 2019, Anup Patel <Anup.Patel@wdc.com> wrote: > >> > >> > Like I mentioned, there is no functional issue with this series. > >> > The warm-boot issues were fixed in OpenSBI. > >> > > >> > @Andreas, please try at your end. > >> > >> As long as issue#65 isn't fixed opensbi is mostly a no-go for me. At > >> least it gives me more reasons to press the reset button. :-) > > > > The reset button works fine for me an Atish. I am sure it works fine > > for lot of other folks too. > > > > BTW, as-per discussion with SiFive folks the reset button on Unleashed > > Board is not much tested and it can misbehave on certain boards. It is > > quite possible that you might have a "flaky" board. > > I don't think the reset button differs between boards. As far as I know, the > issues are really just that it doesn't reset everything -- specifically some of > the IP on the chip (clock, power, JTAG) isn't reset and nothing on the board > (SD, ethernet, PCIe, etc) is reset. This frequently results in flakiness when > debugging drivers, but the cores and memory system should all be OK. > > Is that issue 65 on github.com/opensbi? If so it clearly says this isn't a reset > button issue. The issue#65 on githuh.com/opensbi is not a clearly defined and it went in various directions. We tried various things suggested by Andreas and we were only able to replicate issue with reset-button press. This fixed now and reset-button press works perfectly fine with OpenSBI. Apart from reset-button thingy, we tried all other things reported by Andreas but we were not able to reproduce issue at our end. Regards, Anup