| Message ID | 1504132707-10406-4-git-send-email-arbab@linux.vnet.ibm.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | npu2: PHY initialization updates | expand |
On 31/08/17 08:38, Reza Arbab wrote: > Per the updated programming guide (procedure 1.2.4), set > rx_pr_edge_track_cntl and rx_pr_fw_off appropriately before and after > calibration. > > Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> This matches what we've been doing internally for OpenCAPI bringup. Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > --- > hw/npu2-hw-procedures.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c > index 5ccc1a0..a140aed 100644 > --- a/hw/npu2-hw-procedures.c > +++ b/hw/npu2-hw-procedures.c > @@ -59,6 +59,8 @@ struct npu2_phy_reg NPU2_PHY_TX_UNLOAD_CLK_DISABLE = {0x103, 56, 1}; > struct npu2_phy_reg NPU2_PHY_TX_FIFO_INIT = {0x105, 53, 1}; > struct npu2_phy_reg NPU2_PHY_TX_RXCAL = {0x103, 57, 1}; > struct npu2_phy_reg NPU2_PHY_RX_INIT_DONE = {0x0ca, 48, 1}; > +struct npu2_phy_reg NPU2_PHY_RX_PR_EDGE_TRACK_CNTL = {0x092, 48, 2}; > +struct npu2_phy_reg NPU2_PHY_RX_PR_FW_OFF = {0x08a, 56, 1}; > > /* These registers are per-PHY, not per lane */ > struct npu2_phy_reg NPU2_PHY_TX_ZCAL_SWO_EN = {0x3c9, 48, 1}; > @@ -521,6 +523,9 @@ static uint32_t phy_rx_dccal(struct npu2_dev *ndev) > int lane; > > FOR_EACH_LANE(ndev, lane) > + phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1); > + > + FOR_EACH_LANE(ndev, lane) > phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 1); Could probably put these in the same FOR_EACH_LANE block? > > return PROCEDURE_NEXT; > @@ -537,8 +542,11 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev) > FOR_EACH_LANE(ndev, lane) > phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 0); > > - FOR_EACH_LANE(ndev, lane) > + FOR_EACH_LANE(ndev, lane) { > phy_write_lane(ndev, &NPU2_PHY_RX_B_BANK_CONTROLS, lane, 0); > + phy_write_lane(ndev, &NPU2_PHY_RX_PR_EDGE_TRACK_CNTL, lane, 0); > + phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0); > + } > > return PROCEDURE_NEXT; > } >
On Thu, Aug 31, 2017 at 01:11:30PM +1000, Andrew Donnellan wrote: >On 31/08/17 08:38, Reza Arbab wrote: >>@@ -521,6 +523,9 @@ static uint32_t phy_rx_dccal(struct npu2_dev *ndev) >> int lane; >> FOR_EACH_LANE(ndev, lane) >>+ phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1); >>+ >>+ FOR_EACH_LANE(ndev, lane) >> phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 1); > >Could probably put these in the same FOR_EACH_LANE block? Well, the pseudocode in the programming guide does separate loops for each item like this. Maybe I'm cargo culting, but it seems significant because right below, it does three items in the same loop: >>@@ -537,8 +542,11 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev) >> FOR_EACH_LANE(ndev, lane) >> phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 0); >>- FOR_EACH_LANE(ndev, lane) >>+ FOR_EACH_LANE(ndev, lane) { >> phy_write_lane(ndev, &NPU2_PHY_RX_B_BANK_CONTROLS, lane, 0); >>+ phy_write_lane(ndev, &NPU2_PHY_RX_PR_EDGE_TRACK_CNTL, lane, 0); >>+ phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0); >>+ } >> return PROCEDURE_NEXT; >> }
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 5ccc1a0..a140aed 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -59,6 +59,8 @@ struct npu2_phy_reg NPU2_PHY_TX_UNLOAD_CLK_DISABLE = {0x103, 56, 1}; struct npu2_phy_reg NPU2_PHY_TX_FIFO_INIT = {0x105, 53, 1}; struct npu2_phy_reg NPU2_PHY_TX_RXCAL = {0x103, 57, 1}; struct npu2_phy_reg NPU2_PHY_RX_INIT_DONE = {0x0ca, 48, 1}; +struct npu2_phy_reg NPU2_PHY_RX_PR_EDGE_TRACK_CNTL = {0x092, 48, 2}; +struct npu2_phy_reg NPU2_PHY_RX_PR_FW_OFF = {0x08a, 56, 1}; /* These registers are per-PHY, not per lane */ struct npu2_phy_reg NPU2_PHY_TX_ZCAL_SWO_EN = {0x3c9, 48, 1}; @@ -521,6 +523,9 @@ static uint32_t phy_rx_dccal(struct npu2_dev *ndev) int lane; FOR_EACH_LANE(ndev, lane) + phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1); + + FOR_EACH_LANE(ndev, lane) phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 1); return PROCEDURE_NEXT; @@ -537,8 +542,11 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev) FOR_EACH_LANE(ndev, lane) phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 0); - FOR_EACH_LANE(ndev, lane) + FOR_EACH_LANE(ndev, lane) { phy_write_lane(ndev, &NPU2_PHY_RX_B_BANK_CONTROLS, lane, 0); + phy_write_lane(ndev, &NPU2_PHY_RX_PR_EDGE_TRACK_CNTL, lane, 0); + phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0); + } return PROCEDURE_NEXT; }
Per the updated programming guide (procedure 1.2.4), set rx_pr_edge_track_cntl and rx_pr_fw_off appropriately before and after calibration. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> --- hw/npu2-hw-procedures.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)