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[2/3] npu2: hw-procedures: Change rx_pr_phase_step value

Message ID 1504132707-10406-3-git-send-email-arbab@linux.vnet.ibm.com
State Accepted
Headers show
Series npu2: PHY initialization updates | expand

Commit Message

Reza Arbab Aug. 30, 2017, 10:38 p.m. UTC
Change this value, per the updated programming guide.

Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
---
 hw/npu2-hw-procedures.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alistair Popple Aug. 31, 2017, 7:06 a.m. UTC | #1
Matches the docs, thanks.

Acked-By: Alistair Popple <alistair@popple.id.au>

On Wed, 30 Aug 2017 05:38:26 PM Reza Arbab wrote:
> Change this value, per the updated programming guide.
> 
> Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
> ---
>  hw/npu2-hw-procedures.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
> index ac5c919..5ccc1a0 100644
> --- a/hw/npu2-hw-procedures.c
> +++ b/hw/npu2-hw-procedures.c
> @@ -304,7 +304,7 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev)
>  		phy_write_lane(ndev, &NPU2_PHY_RX_LANE_ANA_PDWN, lane, 0);
>  		phy_write_lane(ndev, &NPU2_PHY_RX_LANE_DIG_PDWN, lane, 0);
>  		phy_write_lane(ndev, &NPU2_PHY_RX_PR_IQ_RES_SEL, lane, 0x7);
> -		phy_write_lane(ndev, &NPU2_PHY_RX_PR_PHASE_STEP, lane, 0x8);
> +		phy_write_lane(ndev, &NPU2_PHY_RX_PR_PHASE_STEP, lane, 0xc);
>  		phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
>  	}
>  
>
diff mbox series

Patch

diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index ac5c919..5ccc1a0 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -304,7 +304,7 @@  static uint32_t phy_reset_complete(struct npu2_dev *ndev)
 		phy_write_lane(ndev, &NPU2_PHY_RX_LANE_ANA_PDWN, lane, 0);
 		phy_write_lane(ndev, &NPU2_PHY_RX_LANE_DIG_PDWN, lane, 0);
 		phy_write_lane(ndev, &NPU2_PHY_RX_PR_IQ_RES_SEL, lane, 0x7);
-		phy_write_lane(ndev, &NPU2_PHY_RX_PR_PHASE_STEP, lane, 0x8);
+		phy_write_lane(ndev, &NPU2_PHY_RX_PR_PHASE_STEP, lane, 0xc);
 		phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
 	}