| Message ID | 561cef1576dc530c19cff5eea41e7548b948b976.1433180153.git.peter.crosthwaite@xilinx.com |
|---|---|
| State | New |
| Headers | show |
On 1 June 2015 at 19:04, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > These CPs are defined for R5 but don't have a lot of meaning in QEMU > yet. Raz them so the guest can proceed if they are read. The TCM > registers will return a size of 0, indicating no TCM. > > Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> > --- > target-arm/cpu.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index 4872d9c..3538802 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -794,6 +794,17 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) > cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; > } > > +static const ARMCPRegInfo cortexr5_cp_reginfo[] = { > + /* Dummy the TCM region regs for the moment */ > + { .name = "ATCM", .cp = 15, .crn = 9, .crm = 1, .opc1 = 0, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_CONST }, > + { .name = "BTCM", .cp = 15, .crn = 9, .crm = 1, .opc1 = 0, .opc2 = 1, > + .access = PL1_RW, .type = ARM_CP_CONST }, Preferred ordering is cp, opc1, crn, crm, opc2 (same as MRC/MCR insns). > + { .name = "DCIALLU", .cp = 15, .crn = 15, .crm = 5, .opc1 = 0, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_NOP }, I can't find this in the R5 TRM? > + REGINFO_SENTINEL > +}; > + > static void cortex_r5_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > @@ -818,6 +829,7 @@ static void cortex_r5_initfn(Object *obj) > cpu->id_isar3 = 0x01112131; > cpu->id_isar4 = 0x0010142; > cpu->id_isar5 = 0x0; > + define_arm_cp_regs(cpu, cortexr5_cp_reginfo); > } > > static const ARMCPRegInfo cortexa8_cp_reginfo[] = { thanks -- PMM
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4872d9c..3538802 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -794,6 +794,17 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; } +static const ARMCPRegInfo cortexr5_cp_reginfo[] = { + /* Dummy the TCM region regs for the moment */ + { .name = "ATCM", .cp = 15, .crn = 9, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST }, + { .name = "BTCM", .cp = 15, .crn = 9, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST }, + { .name = "DCIALLU", .cp = 15, .crn = 15, .crm = 5, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_NOP }, + REGINFO_SENTINEL +}; + static void cortex_r5_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -818,6 +829,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_isar3 = 0x01112131; cpu->id_isar4 = 0x0010142; cpu->id_isar5 = 0x0; + define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
These CPs are defined for R5 but don't have a lot of meaning in QEMU yet. Raz them so the guest can proceed if they are read. The TCM registers will return a size of 0, indicating no TCM. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> --- target-arm/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)