| Message ID | 20240507130349.86851-2-sebastian.huber@embedded-brains.de |
|---|---|
| State | New |
| Headers | show |
| Series | Zynq 7000 SoC improvements | expand |
On Tue, 7 May 2024 at 14:04, Sebastian Huber <sebastian.huber@embedded-brains.de> wrote: > > The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the > corresponding Qemu device to the xilinx-zynq-a9 machine. > > Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> > --- > hw/arm/xilinx_zynq.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c > index 3190cc0b8d..078abd77bd 100644 > --- a/hw/arm/xilinx_zynq.c > +++ b/hw/arm/xilinx_zynq.c > @@ -242,6 +242,7 @@ static void zynq_init(MachineState *machine) > busdev = SYS_BUS_DEVICE(dev); > sysbus_realize_and_unref(busdev, &error_fatal); > sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); > + sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); > sysbus_connect_irq(busdev, 0, > qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); If we add the cache controller to this board we also need to update the board's entry in hw/arm/Kconfig to add a "select PL310" line. This ensures that if the user asks to build the zynq board type then we will also compile in the PL310 device. thanks -- PMM
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3190cc0b8d..078abd77bd 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -242,6 +242,7 @@ static void zynq_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); + sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+)