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[PULL,00/65] riscv-to-apply queue

Message ID 20240110085733.1607526-1-alistair.francis@wdc.com
State New
Headers show

Pull-request

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240110

Message

Alistair Francis Jan. 10, 2024, 8:56 a.m. UTC 
The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac:

  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-01-09 10:32:23 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240110

for you to fetch changes up to 71b76da33a1558bcd59100188f5753737ef6fa21:

  target/riscv: Ensure mideleg is set correctly on reset (2024-01-10 18:47:47 +1000)

----------------------------------------------------------------
RISC-V PR for 9.0

* Make vector whole-register move (vmv) depend on vtype register
* Fix th.dcache.cval1 priviledge check
* Don't allow write mstatus_vs without RVV
* Use hwaddr instead of target_ulong for RV32
* Fix machine IDs QOM getters\
* Fix KVM reg id sizes
* ACPI: Enable AIA, PLIC and update RHCT
* Fix the interrupts-extended property format of PLIC
* Add support for Zacas extension
* Add amocas.[w,d,q] instructions
* Document acpi parameter of virt machine
* RVA22 profiles support
* Remove group setting of KVM AIA if the machine only has 1 socket
* Add RVV CSRs to KVM
* sifive_u: Update S-mode U-Boot image build instructions
* Upgrade OpenSBI from v1.3.1 to v1.4
* pmp: Ignore writes when RW=01 and MML=0
* Assert that the CSR numbers will be correct
* Don't adjust vscause for exceptions
* Ensure mideleg is set correctly on reset

----------------------------------------------------------------
Alistair Francis (3):
      target/riscv: Assert that the CSR numbers will be correct
      target/riscv: Don't adjust vscause for exceptions
      target/riscv: Ensure mideleg is set correctly on reset

Bin Meng (2):
      docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
      roms/opensbi: Upgrade from v1.3.1 to v1.4

Daniel Henrique Barboza (36):
      target/riscv/cpu.c: fix machine IDs getters
      target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
      target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64
      target/riscv/kvm: change timer regs size to u64
      target/riscv/kvm: add RISCV_CONFIG_REG()
      target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()
      target/riscv: create TYPE_RISCV_VENDOR_CPU
      target/riscv/tcg: do not use "!generic" CPU checks
      target/riscv/tcg: update priv_ver on user_set extensions
      target/riscv: add rv64i CPU
      target/riscv: add zicbop extension flag
      target/riscv/tcg: add 'zic64b' support
      riscv-qmp-cmds.c: expose named features in cpu_model_expansion
      target/riscv: add rva22u64 profile definition
      target/riscv/kvm: add 'rva22u64' flag as unavailable
      target/riscv/tcg: add user flag for profile support
      target/riscv/tcg: add MISA user options hash
      target/riscv/tcg: add riscv_cpu_write_misa_bit()
      target/riscv/tcg: handle profile MISA bits
      target/riscv/tcg: add hash table insert helpers
      target/riscv/tcg: honor user choice for G MISA bits
      target/riscv/tcg: validate profiles during finalize
      riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
      target/riscv: add 'rva22u64' CPU
      target/riscv: implement svade
      target/riscv: add priv ver restriction to profiles
      target/riscv/cpu.c: finalize satp_mode earlier
      target/riscv/cpu.c: add riscv_cpu_is_32bit()
      target/riscv: add satp_mode profile support
      target/riscv: add 'parent' in profile description
      target/riscv: add RVA22S64 profile
      target/riscv: add rva22s64 cpu
      linux-headers: Update to Linux v6.7-rc5
      linux-headers: riscv: add ptrace.h
      target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
      target/riscv/kvm: add RVV and Vector CSR regs

Heinrich Schuchardt (1):
      docs/system/riscv: document acpi parameter of virt machine

Ivan Klokov (2):
      target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
      target/riscv: pmp: Ignore writes when RW=01 and MML=0

LIU Zhiwei (2):
      target/riscv: Fix th.dcache.cval1 priviledge check
      target/riscv: Not allow write mstatus_vs without RVV

Max Chou (2):
      target/riscv: Add vill check for whole vector register move instructions
      target/riscv: The whole vector register move instructions depend on vsew

Rob Bradford (1):
      disas/riscv: Add amocas.[w,d,q] instructions

Sunil V L (13):
      hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
      hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
      hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT
      hw/riscv: virt: Make few IMSIC macros and functions public
      hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
      hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
      hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
      hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
      hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
      hw/pci-host/gpex: Define properties for MMIO ranges
      hw/riscv/virt: Update GPEX MMIO related properties
      hw/riscv/virt-acpi-build.c: Add IO controllers and devices
      hw/riscv/virt-acpi-build.c: Add PLIC in MADT

Weiwei Li (1):
      target/riscv: Add support for Zacas extension

Yong-Xuan Wang (2):
      hw/riscv/virt.c: fix the interrupts-extended property format of PLIC
      target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket

 docs/system/riscv/sifive_u.rst                 |  33 +-
 docs/system/riscv/virt.rst                     |   5 +
 include/hw/nvram/fw_cfg_acpi.h                 |  15 +
 include/hw/pci-host/gpex.h                     |  28 +-
 include/hw/riscv/virt.h                        |  26 ++
 include/hw/virtio/virtio-acpi.h                |  16 +
 include/standard-headers/drm/drm_fourcc.h      |   2 +
 include/standard-headers/linux/pci_regs.h      |  24 +-
 include/standard-headers/linux/vhost_types.h   |   7 +
 include/standard-headers/linux/virtio_config.h |   5 +
 include/standard-headers/linux/virtio_pci.h    |  11 +
 linux-headers/asm-arm64/kvm.h                  |  32 ++
 linux-headers/asm-generic/unistd.h             |  14 +-
 linux-headers/asm-loongarch/bitsperlong.h      |   1 +
 linux-headers/asm-loongarch/kvm.h              | 108 ++++++
 linux-headers/asm-loongarch/mman.h             |   1 +
 linux-headers/asm-loongarch/unistd.h           |   5 +
 linux-headers/asm-mips/unistd_n32.h            |   4 +
 linux-headers/asm-mips/unistd_n64.h            |   4 +
 linux-headers/asm-mips/unistd_o32.h            |   4 +
 linux-headers/asm-powerpc/unistd_32.h          |   4 +
 linux-headers/asm-powerpc/unistd_64.h          |   4 +
 linux-headers/asm-riscv/kvm.h                  |  12 +
 linux-headers/asm-riscv/ptrace.h               | 132 +++++++
 linux-headers/asm-s390/unistd_32.h             |   4 +
 linux-headers/asm-s390/unistd_64.h             |   4 +
 linux-headers/asm-x86/unistd_32.h              |   4 +
 linux-headers/asm-x86/unistd_64.h              |   3 +
 linux-headers/asm-x86/unistd_x32.h             |   3 +
 linux-headers/linux/iommufd.h                  | 180 +++++++++-
 linux-headers/linux/kvm.h                      |  11 +
 linux-headers/linux/psp-sev.h                  |   1 +
 linux-headers/linux/stddef.h                   |   9 +-
 linux-headers/linux/userfaultfd.h              |   9 +-
 linux-headers/linux/vfio.h                     |  47 ++-
 linux-headers/linux/vhost.h                    |   8 +
 target/riscv/cpu-qom.h                         |   5 +
 target/riscv/cpu.h                             |  18 +
 target/riscv/cpu_cfg.h                         |   5 +
 target/riscv/pmp.h                             |   8 +-
 target/riscv/insn32.decode                     |   6 +
 disas/riscv.c                                  |   9 +
 hw/arm/virt-acpi-build.c                       |  51 +--
 hw/i386/acpi-microvm.c                         |  15 +-
 hw/nvram/fw_cfg-acpi.c                         |  23 ++
 hw/pci-host/gpex-acpi.c                        |  13 +
 hw/pci-host/gpex.c                             |  12 +
 hw/riscv/virt-acpi-build.c                     | 323 ++++++++++++++++--
 hw/riscv/virt.c                                | 124 +++----
 hw/virtio/virtio-acpi.c                        |  33 ++
 target/riscv/cpu.c                             | 223 ++++++++++--
 target/riscv/cpu_helper.c                      |   4 +-
 target/riscv/csr.c                             |  10 +-
 target/riscv/kvm/kvm-cpu.c                     | 250 ++++++++++----
 target/riscv/pmp.c                             |  28 +-
 target/riscv/riscv-qmp-cmds.c                  |  44 ++-
 target/riscv/tcg/tcg-cpu.c                     | 455 ++++++++++++++++++++++---
 target/riscv/translate.c                       |   1 +
 target/riscv/insn_trans/trans_rvv.c.inc        |   8 +-
 target/riscv/insn_trans/trans_rvzacas.c.inc    | 150 ++++++++
 target/riscv/insn_trans/trans_xthead.c.inc     |   2 +-
 hw/nvram/meson.build                           |   1 +
 hw/riscv/Kconfig                               |   1 +
 hw/virtio/meson.build                          |   1 +
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 135376 -> 267416 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 138368 -> 270808 bytes
 roms/opensbi                                   |   2 +-
 scripts/update-linux-headers.sh                |   3 +
 68 files changed, 2248 insertions(+), 360 deletions(-)
 create mode 100644 include/hw/nvram/fw_cfg_acpi.h
 create mode 100644 include/hw/virtio/virtio-acpi.h
 create mode 100644 linux-headers/asm-loongarch/bitsperlong.h
 create mode 100644 linux-headers/asm-loongarch/kvm.h
 create mode 100644 linux-headers/asm-loongarch/mman.h
 create mode 100644 linux-headers/asm-loongarch/unistd.h
 create mode 100644 linux-headers/asm-riscv/ptrace.h
 create mode 100644 hw/nvram/fw_cfg-acpi.c
 create mode 100644 hw/virtio/virtio-acpi.c
 create mode 100644 target/riscv/insn_trans/trans_rvzacas.c.inc

Comments

Peter Maydell Jan. 10, 2024, 4:21 p.m. UTC | #1 
On Wed, 10 Jan 2024 at 08:58, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac:
>
>   Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-01-09 10:32:23 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240110
>
> for you to fetch changes up to 71b76da33a1558bcd59100188f5753737ef6fa21:
>
>   target/riscv: Ensure mideleg is set correctly on reset (2024-01-10 18:47:47 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.0
>
> * Make vector whole-register move (vmv) depend on vtype register
> * Fix th.dcache.cval1 priviledge check
> * Don't allow write mstatus_vs without RVV
> * Use hwaddr instead of target_ulong for RV32
> * Fix machine IDs QOM getters\
> * Fix KVM reg id sizes
> * ACPI: Enable AIA, PLIC and update RHCT
> * Fix the interrupts-extended property format of PLIC
> * Add support for Zacas extension
> * Add amocas.[w,d,q] instructions
> * Document acpi parameter of virt machine
> * RVA22 profiles support
> * Remove group setting of KVM AIA if the machine only has 1 socket
> * Add RVV CSRs to KVM
> * sifive_u: Update S-mode U-Boot image build instructions
> * Upgrade OpenSBI from v1.3.1 to v1.4
> * pmp: Ignore writes when RW=01 and MML=0
> * Assert that the CSR numbers will be correct
> * Don't adjust vscause for exceptions
> * Ensure mideleg is set correctly on reset
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.

-- PMM