@@ -3087,5 +3087,5 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/*
* Note that XZR cannot be encoded in the address base register slot,
- * as that actaully encodes SP. Depending on the guest, we may need
+ * as that actually encodes SP. Depending on the guest, we may need
* to zero-extend the guest address via the address index register slot,
* therefore we need to load even a zero guest base into a register.
@@ -1217,5 +1217,5 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
case TCG_COND_GTU:
case TCG_COND_GEU:
- /* We perform a conditional comparision. If the high half is
+ /* We perform a conditional comparison. If the high half is
equal, then overwrite the flags with the comparison of the
low half. The resulting flags cover the whole. */
@@ -1251,5 +1251,5 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
/*
* Note that TCGReg references Q-registers.
- * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+ * Q-regno = 2 * D-regno, so shift left by 1 while inserting.
*/
static uint32_t encode_vd(TCGReg rd)
@@ -70,5 +70,5 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers */
- /* TCG_REG_S0 reservered for TCG_AREG0 */
+ /* TCG_REG_S0 reserved for TCG_AREG0 */
TCG_REG_S1,
TCG_REG_S2,
@@ -261,5 +261,5 @@ typedef enum {
OPC_ADD_UW = 0x0800003b,
- /* Zbb: Bit manipulation extension, basic bit manipulaton */
+ /* Zbb: Bit manipulation extension, basic bit manipulation */
OPC_ANDN = 0x40007033,
OPC_CLZ = 0x60001013,
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> --- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/riscv/tcg-target.c.inc | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)