@@ -43,5 +43,5 @@ static void latch_registers(CXLDownstreamPort *dsp)
}
-/* TODO: Look at sharing this code acorss all CXL port types */
+/* TODO: Look at sharing this code across all CXL port types */
static void cxl_dsp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
uint32_t val, int len)
@@ -264,5 +264,5 @@ static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
/*
* First carry out normal swizzle to handle
- * multple root ports on a pxb instance.
+ * multiple root ports on a pxb instance.
*/
pin = pci_swizzle_map_irq_fn(pci_dev, pin);
@@ -63,5 +63,5 @@
#endif
-/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
+/* from linux source code. include/asm-mips/mips-boards/bonito64.h*/
#define BONITO_BOOT_BASE 0x1fc00000
#define BONITO_BOOT_SIZE 0x00100000
@@ -489,5 +489,5 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
/*
* If no inbound iATU windows are configured, HW defaults to
- * letting inbound TLPs to pass in. We emulate that by exlicitly
+ * letting inbound TLPs to pass in. We emulate that by explicitly
* configuring first inbound window to cover all of target's
* address space.
@@ -504,5 +504,5 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
root, "pcie-msi", 0x4);
/*
- * We initially place MSI interrupt I/O region a adress 0 and
+ * We initially place MSI interrupt I/O region a address 0 and
* disable it. It'll be later moved to correct offset and enabled
* in designware_pcie_root_update_msi_mapping() as a part of
@@ -1,4 +1,4 @@
/*
- * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
+ * HP-PARISC Dino PCI chipset emulation, as in B160L and similar machines
*
* (C) 2017-2019 by Helge Deller <deller@gmx.de>
@@ -178,5 +178,5 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
/*
- * Resources defined for PXBs are composed by the folling parts:
+ * Resources defined for PXBs are composed by the following parts:
* 1. The resources the pci-brige/pcie-root-port need.
* 2. The resources the devices behind pxb need.
@@ -332,7 +332,7 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
* The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
* Command Register determines how data transactions from the CPU to/from
- * PCI are handled along with the setting of the Endianess bit in the CPU
+ * PCI are handled along with the setting of the Endianness bit in the CPU
* Configuration Register. See:
- * - Table 16: 32-bit PCI Transaction Endianess
+ * - Table 16: 32-bit PCI Transaction Endianness
* - Table 158: PCI_0 Command, Offset: 0xc00
*/
@@ -26,5 +26,5 @@
* Otherwise use object_typename[index] as QOM id.
*
- * This helper does both operations at the same time because seting
+ * This helper does both operations at the same time because setting
* a new QOM child will erase the bus parent of the device. This happens
* because object_unparent() will call object_property_del_child(),
@@ -758,5 +758,5 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr,
*
* TODO: Venice/Murano support it on bottom window above 4G and
- * Naples suports it on everything
+ * Naples supports it on everything
*/
if (!(tve & PPC_BIT(51))) {
@@ -282,5 +282,5 @@ static void phb3_msi_instance_init(Object *obj)
OBJ_PROP_LINK_STRONG);
- /* Will be overriden later */
+ /* Will be overridden later */
ics->offset = 0;
}
@@ -208,5 +208,5 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index)
}
- /* TODO: Figure out how to implemet/decode AOMASK */
+ /* TODO: Figure out how to implement/decode AOMASK */
/* Check if it matches an enabled MMIO region in the PEC stack */
@@ -392,5 +392,5 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val)
*tptr = val;
- /* Copy accross the valid bit to the other half */
+ /* Copy across the valid bit to the other half */
phb->ioda_MBT[idx ^ 1] &= 0x7fffffffffffffffull;
phb->ioda_MBT[idx ^ 1] |= 0x8000000000000000ull & val;
@@ -1409,5 +1409,5 @@ static void pnv_phb4_msi_write(void *opaque, hwaddr addr,
}
- /* TODO: check PE/MSI assignement */
+ /* TODO: check PE/MSI assignment */
qemu_irq_pulse(phb->qirqs[src]);
@@ -325,5 +325,5 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
* So just discard the error for now.
* OS which cares of aer would receive errors via
- * native aer mechanims, so this wouldn't matter.
+ * native aer mechanisms, so this wouldn't matter.
*/
}
@@ -616,5 +616,5 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar,
if (nslots > SHPC_MAX_SLOTS ||
SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
- /* TODO: report an error mesage that makes sense. */
+ /* TODO: report an error message that makes sense. */
return -EINVAL;
}
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> --- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci-host/bonito.c | 2 +- hw/pci-host/designware.c | 4 ++-- hw/pci-host/dino.c | 2 +- hw/pci-host/gpex-acpi.c | 2 +- hw/pci-host/gt64120.c | 4 ++-- hw/pci-host/pnv_phb.c | 2 +- hw/pci-host/pnv_phb3.c | 2 +- hw/pci-host/pnv_phb3_msi.c | 2 +- hw/pci-host/pnv_phb4.c | 6 +++--- hw/pci/pcie_aer.c | 2 +- hw/pci/shpc.c | 2 +- 13 files changed, 17 insertions(+), 17 deletions(-)