diff mbox series

[RFC,v2,04/44] target/loongarch: Add CHECK_SXE maccro for check LSX enable

Message ID 20230328030631.3117129-5-gaosong@loongson.cn
State New
Headers show
Series Add LoongArch LSX instructions | expand

Commit Message

gaosong March 28, 2023, 3:05 a.m. UTC
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu.c                      |  2 ++
 target/loongarch/cpu.h                      |  2 ++
 target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++++++++++
 3 files changed, 15 insertions(+)

Comments

Richard Henderson March 28, 2023, 7:42 p.m. UTC | #1
On 3/27/23 20:05, Song Gao wrote:
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -52,6 +52,7 @@ static const char * const excp_names[] = {
>       [EXCCODE_FPE] = "Floating Point Exception",
>       [EXCCODE_DBP] = "Debug breakpoint",
>       [EXCCODE_BCE] = "Bound Check Exception",
> +    [EXCCODE_SXD] = "128 bit vector instructions Disable exception",
>   };
>   
>   const char *loongarch_exception_name(int32_t exception)
> @@ -187,6 +188,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
>       case EXCCODE_FPD:
>       case EXCCODE_FPE:
>       case EXCCODE_BCE:
> +    case EXCCODE_ASXD:

SXD?

 From what little documentation is present in Volume 1, ASXD appears to be for a 256-bit 
vector extension?


r~
gaosong March 29, 2023, 2:28 a.m. UTC | #2
在 2023/3/29 上午3:42, Richard Henderson 写道:
> On 3/27/23 20:05, Song Gao wrote:
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -52,6 +52,7 @@ static const char * const excp_names[] = {
>>       [EXCCODE_FPE] = "Floating Point Exception",
>>       [EXCCODE_DBP] = "Debug breakpoint",
>>       [EXCCODE_BCE] = "Bound Check Exception",
>> +    [EXCCODE_SXD] = "128 bit vector instructions Disable exception",
>>   };
>>     const char *loongarch_exception_name(int32_t exception)
>> @@ -187,6 +188,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
>>       case EXCCODE_FPD:
>>       case EXCCODE_FPE:
>>       case EXCCODE_BCE:
>> +    case EXCCODE_ASXD:
>
> SXD?
>
Oh,  Should be SXD.
> From what little documentation is present in Volume 1, ASXD appears to 
> be for a 256-bit vector extension?
>
Yes.

Thanks.
Song Gao
diff mbox series

Patch

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 2263bd4fdd..a3ce1ccf00 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -52,6 +52,7 @@  static const char * const excp_names[] = {
     [EXCCODE_FPE] = "Floating Point Exception",
     [EXCCODE_DBP] = "Debug breakpoint",
     [EXCCODE_BCE] = "Bound Check Exception",
+    [EXCCODE_SXD] = "128 bit vector instructions Disable exception",
 };
 
 const char *loongarch_exception_name(int32_t exception)
@@ -187,6 +188,7 @@  static void loongarch_cpu_do_interrupt(CPUState *cs)
     case EXCCODE_FPD:
     case EXCCODE_FPE:
     case EXCCODE_BCE:
+    case EXCCODE_ASXD:
         env->CSR_BADV = env->pc;
         QEMU_FALLTHROUGH;
     case EXCCODE_ADEM:
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 6e5fa6a01d..2e5326f474 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -429,6 +429,7 @@  static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
 #define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
 #define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
 #define HW_FLAGS_EUEN_FPE   0x04
+#define HW_FLAGS_EUEN_SXE   0x08
 
 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
                                         target_ulong *pc,
@@ -439,6 +440,7 @@  static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
     *cs_base = 0;
     *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
     *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
+    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
 }
 
 void loongarch_cpu_list(void);
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
index 1cf3ab34a9..5dedb044d7 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -3,3 +3,14 @@ 
  * LSX translate functions
  * Copyright (c) 2022-2023 Loongson Technology Corporation Limited
  */
+
+#ifndef CONFIG_USER_ONLY
+#define CHECK_SXE do { \
+    if ((ctx->base.tb->flags & HW_FLAGS_EUEN_SXE) == 0) { \
+        generate_exception(ctx, EXCCODE_SXD); \
+        return true; \
+    } \
+} while (0)
+#else
+#define CHECK_SXE
+#endif